Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 418af4a8 authored by Ray Jui's avatar Ray Jui Committed by Linus Walleij
Browse files

pinctrl: Update iProc GPIO DT bindings 



Update the iProc GPIO binding document to add new compatible strings
"brcm,iproc-nsp-gpio" and "brcm,iproc-stingray-gpio" to support the
iProc based GPIO controller used in the NSP and Stingray SoCs,
respectively

Signed-off-by: default avatarRay Jui <ray.jui@broadcom.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 53056f59

Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt

+16 −2
Original line number Original line Diff line number Diff line
@@ -3,8 +3,22 @@ Broadcom iProc GPIO/PINCONF Controller 
Required properties:

Required properties:





- compatible:

- compatible:

    Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio",

    "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that

    "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"

    supports full-featured pinctrl and GPIO functions used in various iProc

    based SoCs



    May contain an SoC-specific compatibility string to accommodate any

    SoC-specific features



    "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or

    "brcm,cygnus-crmu-gpio" for Cygnus SoCs



    "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support

    disabled



    "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general

    pinctrl support completely disabled in this IP block. In Stingray, a

    different IP block is used to handle pinctrl related functions





- reg:

- reg:

    Define the base and range of the I/O address space that contains SoC

    Define the base and range of the I/O address space that contains SoC