Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 414abe0a authored by James Smart's avatar James Smart Committed by Martin K. Petersen
Browse files

scsi: lpfc: Make PBDE optimizations configurable



The PBDE optimizations aren't supported in all firmware revs.

Make optimizations configurable in case there's a side effect on old
firmware.

Signed-off-by: default avatarDick Kennedy <dick.kennedy@broadcom.com>
Signed-off-by: default avatarJames Smart <james.smart@broadcom.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 68c9b55d
Loading
Loading
Loading
Loading
+1 −2
Original line number Diff line number Diff line
@@ -840,8 +840,7 @@ struct lpfc_hba {
#define LPFC_ENABLE_FCP  1
#define LPFC_ENABLE_NVME 2
#define LPFC_ENABLE_BOTH 3
	uint32_t nvme_embed_pbde;
	uint32_t fcp_embed_pbde;
	uint32_t cfg_enable_pbde;
	uint32_t io_channel_irqs;	/* number of irqs for io channels */
	struct nvmet_fc_target_port *targetport;
	lpfc_vpd_t vpd;		/* vital product data */
+10 −0
Original line number Diff line number Diff line
@@ -5387,6 +5387,14 @@ LPFC_BBCR_ATTR_RW(enable_bbcr, 1, 0, 1, "Enable BBC Recovery");
 */
LPFC_ATTR_RW(enable_dpp, 1, 0, 1, "Enable Direct Packet Push");

/*
 * lpfc_enable_pbde: Enable PBDE on PRISM - G7
 *       0  = PBDE on G7 disabled
 *       1  = PBDE on G7 enabled (default)
 * Value range is [0,1]. Default value is 1
 */
LPFC_ATTR_R(enable_pbde, 1, 0, 1, "Enable PBDE support on PRISM");

struct device_attribute *lpfc_hba_attrs[] = {
	&dev_attr_nvme_info,
	&dev_attr_bg_info,
@@ -5498,6 +5506,7 @@ struct device_attribute *lpfc_hba_attrs[] = {
	&dev_attr_lpfc_enable_mds_diags,
	&dev_attr_lpfc_enable_bbcr,
	&dev_attr_lpfc_enable_dpp,
	&dev_attr_lpfc_enable_pbde,
	NULL,
};

@@ -6514,6 +6523,7 @@ lpfc_get_cfgparam(struct lpfc_hba *phba)
	lpfc_nvme_io_channel_init(phba, lpfc_nvme_io_channel);
	lpfc_enable_bbcr_init(phba, lpfc_enable_bbcr);
	lpfc_enable_dpp_init(phba, lpfc_enable_dpp);
	lpfc_enable_pbde_init(phba, lpfc_enable_pbde);

	if (phba->sli_rev != LPFC_SLI_REV4) {
		/* NVME only supported on SLI4 */
+7 −15
Original line number Diff line number Diff line
@@ -10673,18 +10673,10 @@ lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
		phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
	}

	/* Only embed PBDE for if_type 6 */
	if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
	    LPFC_SLI_INTF_IF_TYPE_6) {
		phba->fcp_embed_pbde = 1;
		phba->nvme_embed_pbde = 1;
	}

	/* PBDE support requires xib be set */
	if (!bf_get(cfg_xib, mbx_sli4_parameters)) {
		phba->fcp_embed_pbde = 0;
		phba->nvme_embed_pbde = 0;
	}
	/* Only embed PBDE for if_type 6, PBDE support requires xib be set */
	if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
	    LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
		phba->cfg_enable_pbde = 0;

	/*
	 * To support Suppress Response feature we must satisfy 3 conditions.
@@ -10718,10 +10710,10 @@ lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
		phba->fcp_embed_io = 0;

	lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
			"6422 XIB %d: FCP %d %d NVME %d %d %d %d\n",
			"6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
			bf_get(cfg_xib, mbx_sli4_parameters),
			phba->fcp_embed_pbde, phba->fcp_embed_io,
			phba->nvme_support, phba->nvme_embed_pbde,
			phba->cfg_enable_pbde,
			phba->fcp_embed_io, phba->nvme_support,
			phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);

	if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
+4 −4
Original line number Diff line number Diff line
@@ -1279,6 +1279,8 @@ lpfc_nvme_prep_io_cmd(struct lpfc_vport *vport,
	/* Word 9 */
	bf_set(wqe_reqtag, &wqe->generic.wqe_com, pwqeq->iotag);

	/* Words 13 14 15 are for PBDE support */

	pwqeq->vport = vport;
	return 0;
}
@@ -1378,7 +1380,7 @@ lpfc_nvme_prep_io_dma(struct lpfc_vport *vport,
			data_sg = sg_next(data_sg);
			sgl++;
		}
		if (phba->nvme_embed_pbde) {
		if (phba->cfg_enable_pbde) {
			/* Use PBDE support for first SGL only, offset == 0 */
			/* Words 13-15 */
			bde = (struct ulp_bde64 *)
@@ -1394,10 +1396,8 @@ lpfc_nvme_prep_io_dma(struct lpfc_vport *vport,
			memset(&wqe->words[13], 0, (sizeof(uint32_t) * 3));
			bf_set(wqe_pbde, &wqe->generic.wqe_com, 0);
		}
	} else {
		bf_set(wqe_pbde, &wqe->generic.wqe_com, 0);
		memset(&wqe->words[13], 0, (sizeof(uint32_t) * 3));

	} else {
		/* For this clause to be valid, the payload_length
		 * and sg_cnt must zero.
		 */
+13 −10
Original line number Diff line number Diff line
@@ -2493,7 +2493,7 @@ lpfc_nvmet_prep_fcp_wqe(struct lpfc_hba *phba,
			bf_set(wqe_xc, &wqe->fcp_treceive.wqe_com, 0);

		/* Word 11 - set pbde later */
		if (phba->nvme_embed_pbde) {
		if (phba->cfg_enable_pbde) {
			do_pbde = 1;
		} else {
			bf_set(wqe_pbde, &wqe->fcp_treceive.wqe_com, 0);
@@ -2608,9 +2608,9 @@ lpfc_nvmet_prep_fcp_wqe(struct lpfc_hba *phba,
			bf_set(lpfc_sli4_sge_last, sgl, 1);
		sgl->word2 = cpu_to_le32(sgl->word2);
		sgl->sge_len = cpu_to_le32(cnt);
		if (do_pbde && i == 0) {
		if (i == 0) {
			bde = (struct ulp_bde64 *)&wqe->words[13];
			memset(bde, 0, sizeof(struct ulp_bde64));
			if (do_pbde) {
				/* Words 13-15  (PBDE) */
				bde->addrLow = sgl->addr_lo;
				bde->addrHigh = sgl->addr_hi;
@@ -2618,6 +2618,9 @@ lpfc_nvmet_prep_fcp_wqe(struct lpfc_hba *phba,
					le32_to_cpu(sgl->sge_len);
				bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64;
				bde->tus.w = cpu_to_le32(bde->tus.w);
			} else {
				memset(bde, 0, sizeof(struct ulp_bde64));
			}
		}
		sgl++;
		ctxp->offset += cnt;
Loading