Commit 414355a7 authored Jun 04, 2015 by Damien Lespiau Committed by Jani Nikula Jun 12, 2015

drm/i915/skl: Don't warn if reading back DPLL0 is disabled



We can operate with DPLL0 off with CDCLK backed by the 24Mhz reference
clock, and that's a supported configuration. Don't warn when notice
DPLL0 is off then.

We still have a separate warn at boot if cdclk is disabled (because we
don't currently try to handle the case (that shouldn't happen on SKL as
far as I know) where we boot with display not initialized.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

parent a9419e84

drivers/gpu/drm/i915/intel_display.c

+1 −3

Original line number	Diff line number	Diff line
		@@ -6737,10 +6737,8 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
		uint32_t cdctl = I915_READ(CDCLK_CTL);
		uint32_t linkrate;

		if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
		WARN(1, "LCPLL1 not enabled\n");
		if (!(lcpll1 & LCPLL_PLL_ENABLE))
		return 24000; /* 24MHz is the cd freq with NSSC ref */
		}

		if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
		return 540000;