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Commit 412252ac authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-dt-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt 

Merge "The i.MX device tree updates for 4.7" from Shawn Guo:

 - More i.MX6 System-on-Module board support from Ka-Ro electronics:
   tx6s-8xxx, tx6u-8xxx, tx6q-1xxx, tx6ul-00xx.
 - Nitrogen6_MAX QP and Nitrogen6_SoloX board support from Boundary
   Devices.
 - VF610 based ZII development board support.
 - Add SAI interface audio support for i.MX6SX SDB board.
 - A number of random updates on LS1021A and VF610 dts files.
 - A couple of pinumx updates on i.MX25 and i.MX28.

* tag 'imx-dt-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (36 commits)
  ARM: dts: imx6qdl-udoo: add 7 inch LCD touchscreen panel support
  ARM: dts: i.MX3x: add keypad port devicetree nodes
  ARM: dts: ls1021a: add pix clock to DCU dts node
  ARM: dts: ls1021a: DSPI has 6 chip-selects
  ARM: dts: ls1021a: Add gpio support for ls1021a platform
  ARM: dts: imx6q-ba16: Remove unused vqmmc-supply
  ARM: dts: ls1021a: add SCFG MSI dts node
  ARM: dts: imx28: add alternative pinmuxing for mac0
  ARM: dts: imx6q-tbs2910: fix fec reset polarity
  ARM: dts: vf610-zii-dev: Add ZII development board.
  ARM: dts: vfxxx: add missing reg properties
  ARM: dts: vf-colibri: increase NAND clock speed
  ARM: dts: vf-colibri: alias the primary FEC as ethernet0
  ARM: dts: imx6sx-sdb: Add SAI support
  bindings: fsl-imx-sdma: Document 'fsl,sdma-event-remap' property
  ARM: dts: imx6sx: Remove unused property
  ARM: dts: imx6sx: Fix SAI DMA index
  ARM: dts: imx6q-ba16: Disable pwm2 by default
  ARM: dts: imx: add Boundary Devices Nitrogen6_SoloX board
  ARM: dts: imx6qdl-sabresd: Pass the hannstar panel compatible string
  ...
parents a5cc8c3a 880e1509

Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt

+27 −0
Original line number Diff line number Diff line
@@ -58,6 +58,15 @@ The third cell specifies the transfer priority as below. 
	1	Medium

	2	Low



Optional properties:



- gpr : The phandle to the General Purpose Register (GPR) node.

- fsl,sdma-event-remap : Register bits of sdma event remap, the format is

  <reg shift val>.

    reg is the GPR register offset.

    shift is the bit position inside the GPR register.

    val is the value of the bit (0 or 1).



Examples:



sdma@83fb0000 {
@@ -83,3 +92,21 @@ ssi2: ssi@70014000 { 
	dma-names = "rx", "tx";

	fsl,fifo-depth = <15>;

};



Using the fsl,sdma-event-remap property:



If we want to use SDMA on the SAI1 port on a MX6SX:



&sdma {

	gpr = <&gpr>;

	/* SDMA events remap for SAI1_RX and SAI1_TX */

	fsl,sdma-event-remap = <0 15 1>, <0 16 1>;

};



The fsl,sdma-event-remap property in this case has two values:

- <0 15 1> means that the offset is 0, so GPR0 is the register of the

SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.

Setting bit 15 to 1 selects SAI1_RX.

- <0 16 1> means that the offset is 0, so GPR0 is the register of the

SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.

Setting bit 16 to 1 selects SAI1_TX.

arch/arm/boot/dts/Makefile

+15 −2
Original line number Diff line number Diff line
@@ -324,8 +324,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ 
	imx6dl-sabrelite.dtb \

	imx6dl-sabresd.dtb \

	imx6dl-tx6dl-comtft.dtb \

	imx6dl-tx6s-8034.dtb \

	imx6dl-tx6s-8035.dtb \

	imx6dl-tx6u-801x.dtb \

	imx6dl-tx6u-8033.dtb \

	imx6dl-tx6u-811x.dtb \

	imx6dl-tx6u-81xx-mb7.dtb \

	imx6dl-udoo.dtb \

	imx6dl-wandboard.dtb \

	imx6dl-wandboard-revb1.dtb \
@@ -364,21 +368,29 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ 
	imx6q-tx6q-1010-comtft.dtb \

	imx6q-tx6q-1020.dtb \

	imx6q-tx6q-1020-comtft.dtb \

	imx6q-tx6q-1036.dtb \

	imx6q-tx6q-1110.dtb \

	imx6q-tx6q-11x0-mb7.dtb \

	imx6q-udoo.dtb \

	imx6q-wandboard.dtb \

	imx6q-wandboard-revb1.dtb \

	imx6qp-nitrogen6_max.dtb \

	imx6qp-sabreauto.dtb \

	imx6qp-sabresd.dtb

dtb-$(CONFIG_SOC_IMX6SL) += \

	imx6sl-evk.dtb \

	imx6sl-warp.dtb

dtb-$(CONFIG_SOC_IMX6SX) += \

	imx6sx-nitrogen6sx.dtb \

	imx6sx-sabreauto.dtb \

	imx6sx-sdb-reva.dtb \

	imx6sx-sdb-sai.dtb \

	imx6sx-sdb.dtb

dtb-$(CONFIG_SOC_IMX6UL) += \

	imx6ul-14x14-evk.dtb

	imx6ul-14x14-evk.dtb \

	imx6ul-tx6ul-0010.dtb \

	imx6ul-tx6ul-0011.dtb \

	imx6ul-tx6ul-mainboard.dtb

dtb-$(CONFIG_SOC_IMX7D) += \

	imx7d-cl-som-imx7.dtb \

	imx7d-sbc-imx7.dtb \
@@ -392,7 +404,8 @@ dtb-$(CONFIG_SOC_VF610) += \ 
	vf610m4-colibri.dtb \

	vf610-cosmic.dtb \

	vf610m4-cosmic.dtb \

	vf610-twr.dtb

	vf610-twr.dtb \

	vf610-zii-dev-rev-b.dtb

dtb-$(CONFIG_ARCH_MXS) += \

	imx23-evk.dtb \

	imx23-olinuxino.dtb \

arch/arm/boot/dts/imx25-pinfunc.h

+70 −54
Original line number Diff line number Diff line
@@ -110,20 +110,20 @@ 
#define MX25_PAD_CS4__UART5_CTS			0x054 0x264 0x000 0x13 0x000

#define MX25_PAD_CS4__GPIO_3_20			0x054 0x264 0x000 0x15 0x000



#define MX25_PAD_CS5__CS5			0x058 0x268 0x000 0x10 0x000

#define MX25_PAD_CS5__CS5			0x058 0x268 0x000 0x00 0x000

#define MX25_PAD_CS5__NF_CE2			0x058 0x268 0x000 0x01 0x000

#define MX25_PAD_CS5__UART5_RTS			0x058 0x268 0x574 0x13 0x000

#define MX25_PAD_CS5__GPIO_3_21			0x058 0x268 0x000 0x15 0x000

#define MX25_PAD_CS5__UART5_RTS			0x058 0x268 0x574 0x03 0x000

#define MX25_PAD_CS5__GPIO_3_21			0x058 0x268 0x000 0x05 0x000



#define MX25_PAD_NF_CE0__NF_CE0			0x05c 0x26c 0x000 0x10 0x000

#define MX25_PAD_NF_CE0__GPIO_3_22		0x05c 0x26c 0x000 0x15 0x000



#define MX25_PAD_ECB__ECB			0x060 0x270 0x000 0x10 0x000

#define MX25_PAD_ECB__UART5_TXD_MUX		0x060 0x270 0x000 0x13 0x000

#define MX25_PAD_ECB__UART5_TXD			0x060 0x270 0x000 0x13 0x000

#define MX25_PAD_ECB__GPIO_3_23			0x060 0x270 0x000 0x15 0x000



#define MX25_PAD_LBA__LBA			0x064 0x274 0x000 0x10 0x000

#define MX25_PAD_LBA__UART5_RXD_MUX		0x064 0x274 0x578 0x13 0x000

#define MX25_PAD_LBA__UART5_RXD			0x064 0x274 0x578 0x13 0x000

#define MX25_PAD_LBA__GPIO_3_24			0x064 0x274 0x000 0x15 0x000



#define MX25_PAD_BCLK__BCLK			0x068 0x000 0x000 0x00 0x000
@@ -237,17 +237,21 @@ 
#define MX25_PAD_LD7__GPIO_1_21			0x0e4 0x2dc 0x000 0x15 0x000



#define MX25_PAD_LD8__LD8			0x0e8 0x2e0 0x000 0x10 0x000

#define MX25_PAD_LD8__UART4_RXD			0x0e8 0x2e0 0x570 0x12 0x000

#define MX25_PAD_LD8__FEC_TX_ERR		0x0e8 0x2e0 0x000 0x15 0x000

#define MX25_PAD_LD8__SDHC2_CMD			0x0e8 0x2e0 0x4e0 0x06 0x000



#define MX25_PAD_LD9__LD9			0x0ec 0x2e4 0x000 0x10 0x000

#define MX25_PAD_LD9__UART4_TXD			0x0ec 0x2e4 0x000 0x12 0x000

#define MX25_PAD_LD9__FEC_COL			0x0ec 0x2e4 0x504 0x15 0x001

#define MX25_PAD_LD9__SDHC2_CLK			0x0ec 0x2e4 0x4dc 0x06 0x000



#define MX25_PAD_LD10__LD10			0x0f0 0x2e8 0x000 0x10 0x000

#define MX25_PAD_LD10__FEC_RX_ERR		0x0f0 0x2e8 0x518 0x15 0x001

#define MX25_PAD_LD10__LD10			0x0f0 0x2e8 0x000 0x00 0x000

#define MX25_PAD_LD10__UART4_RTS		0x0f0 0x2e8 0x56c 0x02 0x000

#define MX25_PAD_LD10__FEC_RX_ERR		0x0f0 0x2e8 0x518 0x05 0x001



#define MX25_PAD_LD11__LD11			0x0f4 0x2ec 0x000 0x10 0x000

#define MX25_PAD_LD11__UART4_CTS		0x0f4 0x2ec 0x000 0x12 0x000

#define MX25_PAD_LD11__FEC_RDATA2		0x0f4 0x2ec 0x50c 0x15 0x001

#define MX25_PAD_LD11__SDHC2_DAT1		0x0f4 0x2ec 0x4e8 0x06 0x000
@@ -291,22 +295,22 @@ 
#define MX25_PAD_PWM__USBH2_OC			0x11c 0x314 0x580 0x16 0x001



#define MX25_PAD_CSI_D2__CSI_D2			0x120 0x318 0x000 0x10 0x000

#define MX25_PAD_CSI_D2__UART5_RXD_MUX		0x120 0x318 0x578 0x11 0x001

#define MX25_PAD_CSI_D2__UART5_RXD		0x120 0x318 0x578 0x11 0x001

#define MX25_PAD_CSI_D2__SIM1_CLK0		0x120 0x318 0x000 0x04 0x000

#define MX25_PAD_CSI_D2__GPIO_1_27		0x120 0x318 0x000 0x15 0x000

#define MX25_PAD_CSI_D2__CSPI3_MOSI		0x120 0x318 0x000 0x17 0x000



#define MX25_PAD_CSI_D3__CSI_D3			0x124 0x31c 0x000 0x10 0x000

#define MX25_PAD_CSI_D3__UART5_TXD_MUX		0x124 0x31c 0x000 0x11 0x000

#define MX25_PAD_CSI_D3__UART5_TXD		0x124 0x31c 0x000 0x11 0x000

#define MX25_PAD_CSI_D3__SIM1_RST0		0x124 0x31c 0x000 0x04 0x000

#define MX25_PAD_CSI_D3__GPIO_1_28		0x124 0x31c 0x000 0x15 0x000

#define MX25_PAD_CSI_D3__CSPI3_MISO		0x124 0x31c 0x4b4 0x17 0x001



#define MX25_PAD_CSI_D4__CSI_D4			0x128 0x320 0x000 0x10 0x000

#define MX25_PAD_CSI_D4__UART5_RTS		0x128 0x320 0x574 0x11 0x001

#define MX25_PAD_CSI_D4__CSI_D4			0x128 0x320 0x000 0x00 0x000

#define MX25_PAD_CSI_D4__UART5_RTS		0x128 0x320 0x574 0x01 0x001

#define MX25_PAD_CSI_D4__SIM1_VEN0		0x128 0x320 0x000 0x04 0x000

#define MX25_PAD_CSI_D4__GPIO_1_29		0x128 0x320 0x000 0x15 0x000

#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x000 0x17 0x000

#define MX25_PAD_CSI_D4__GPIO_1_29		0x128 0x320 0x000 0x05 0x000

#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x000 0x07 0x000



#define MX25_PAD_CSI_D5__CSI_D5			0x12c 0x324 0x000 0x10 0x000

#define MX25_PAD_CSI_D5__UART5_CTS		0x12c 0x324 0x000 0x11 0x000
@@ -360,7 +364,7 @@ 
#define MX25_PAD_I2C1_DAT__GPIO_1_13		0x154 0x34c 0x000 0x15 0x000



#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		0x158 0x350 0x000 0x10 0x000

#define MX25_PAD_CSPI1_MOSI__UART3_RXD		0x158 0x350 0x000 0x12 0x000

#define MX25_PAD_CSPI1_MOSI__UART3_RXD		0x158 0x350 0x568 0x12 0x000

#define MX25_PAD_CSPI1_MOSI__GPIO_1_14		0x158 0x350 0x000 0x15 0x000



#define MX25_PAD_CSPI1_MISO__CSPI1_MISO		0x15c 0x354 0x000 0x10 0x000
@@ -371,10 +375,10 @@ 
#define MX25_PAD_CSPI1_SS0__PWM2_PWMO		0x160 0x358 0x000 0x12 0x000

#define MX25_PAD_CSPI1_SS0__GPIO_1_16		0x160 0x358 0x000 0x15 0x000



#define MX25_PAD_CSPI1_SS1__CSPI1_SS1		0x164 0x35c 0x000 0x10 0x000

#define MX25_PAD_CSPI1_SS1__I2C3_DAT		0x164 0x35C 0x528 0x11 0x001

#define MX25_PAD_CSPI1_SS1__UART3_RTS		0x164 0x35c 0x000 0x12 0x000

#define MX25_PAD_CSPI1_SS1__GPIO_1_17		0x164 0x35c 0x000 0x15 0x000

#define MX25_PAD_CSPI1_SS1__CSPI1_SS1		0x164 0x35c 0x000 0x00 0x000

#define MX25_PAD_CSPI1_SS1__I2C3_DAT		0x164 0x35C 0x528 0x01 0x001

#define MX25_PAD_CSPI1_SS1__UART3_RTS		0x164 0x35c 0x000 0x02 0x000

#define MX25_PAD_CSPI1_SS1__GPIO_1_17		0x164 0x35c 0x000 0x05 0x000



#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		0x168 0x360 0x000 0x10 0x000

#define MX25_PAD_CSPI1_SCLK__UART3_CTS		0x168 0x360 0x000 0x12 0x000
@@ -383,20 +387,24 @@ 
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY		0x16c 0x364 0x000 0x10 0x000

#define MX25_PAD_CSPI1_RDY__GPIO_2_22		0x16c 0x364 0x000 0x15 0x000



#define MX25_PAD_UART1_RXD__UART1_RXD		0x170 0x368 0x000 0x10 0x000

#define MX25_PAD_UART1_RXD__GPIO_4_22		0x170 0x368 0x000 0x15 0x000

#define MX25_PAD_UART1_RXD__UART1_RXD		0x170 0x368 0x000 0x00 0x000

#define MX25_PAD_UART1_RXD__UART2_DTR		0x170 0x368 0x000 0x03 0x000

#define MX25_PAD_UART1_RXD__GPIO_4_22		0x170 0x368 0x000 0x05 0x000



#define MX25_PAD_UART1_TXD__UART1_TXD		0x174 0x36c 0x000 0x10 0x000

#define MX25_PAD_UART1_TXD__GPIO_4_23		0x174 0x36c 0x000 0x15 0x000

#define MX25_PAD_UART1_TXD__UART1_TXD		0x174 0x36c 0x000 0x00 0x000

#define MX25_PAD_UART1_TXD__UART2_DSR		0x174 0x36c 0x000 0x03 0x000

#define MX25_PAD_UART1_TXD__GPIO_4_23		0x174 0x36c 0x000 0x05 0x000



#define MX25_PAD_UART1_RTS__UART1_RTS		0x178 0x370 0x000 0x10 0x000

#define MX25_PAD_UART1_RTS__CSI_D0		0x178 0x370 0x488 0x11 0x001

#define MX25_PAD_UART1_RTS__CC3			0x178 0x370 0x000 0x12 0x000

#define MX25_PAD_UART1_RTS__GPIO_4_24		0x178 0x370 0x000 0x15 0x000

#define MX25_PAD_UART1_RTS__UART1_RTS		0x178 0x370 0x000 0x00 0x000

#define MX25_PAD_UART1_RTS__CSI_D0		0x178 0x370 0x488 0x01 0x001

#define MX25_PAD_UART1_RTS__CC3			0x178 0x370 0x000 0x02 0x000

#define MX25_PAD_UART1_RTS__UART2_DCD		0x178 0x370 0x000 0x03 0x000

#define MX25_PAD_UART1_RTS__GPIO_4_24		0x178 0x370 0x000 0x05 0x000



#define MX25_PAD_UART1_CTS__UART1_CTS		0x17c 0x374 0x000 0x10 0x000

#define MX25_PAD_UART1_CTS__CSI_D1		0x17c 0x374 0x48c 0x11 0x001

#define MX25_PAD_UART1_CTS__GPIO_4_25		0x17c 0x374 0x000 0x15 0x000

#define MX25_PAD_UART1_CTS__UART1_CTS		0x17c 0x374 0x000 0x00 0x000

#define MX25_PAD_UART1_CTS__CSI_D1		0x17c 0x374 0x48c 0x01 0x001

#define MX25_PAD_UART1_CTS__UART2_RI		0x17c 0x374 0x000 0x03 0x001

#define MX25_PAD_UART1_CTS__GPIO_4_25		0x17c 0x374 0x000 0x05 0x000



#define MX25_PAD_UART2_RXD__UART2_RXD		0x180 0x378 0x000 0x10 0x000

#define MX25_PAD_UART2_RXD__GPIO_4_26		0x180 0x378 0x000 0x15 0x000
@@ -404,10 +412,10 @@ 
#define MX25_PAD_UART2_TXD__UART2_TXD		0x184 0x37c 0x000 0x10 0x000

#define MX25_PAD_UART2_TXD__GPIO_4_27		0x184 0x37c 0x000 0x15 0x000



#define MX25_PAD_UART2_RTS__UART2_RTS		0x188 0x380 0x000 0x10 0x000

#define MX25_PAD_UART2_RTS__FEC_COL		0x188 0x380 0x504 0x12 0x002

#define MX25_PAD_UART2_RTS__CC1			0x188 0x380 0x000 0x13 0x000

#define MX25_PAD_UART2_RTS__GPIO_4_28		0x188 0x380 0x000 0x15 0x000

#define MX25_PAD_UART2_RTS__UART2_RTS		0x188 0x380 0x000 0x00 0x000

#define MX25_PAD_UART2_RTS__FEC_COL		0x188 0x380 0x504 0x02 0x002

#define MX25_PAD_UART2_RTS__CC1			0x188 0x380 0x000 0x03 0x000

#define MX25_PAD_UART2_RTS__GPIO_4_28		0x188 0x380 0x000 0x05 0x000



#define MX25_PAD_UART2_CTS__UART2_CTS		0x18c 0x384 0x000 0x10 0x000

#define MX25_PAD_UART2_CTS__FEC_RX_ERR		0x18c 0x384 0x518 0x12 0x002
@@ -439,36 +447,42 @@ 
#define MX25_PAD_SD1_DATA3__FEC_CRS		0x1a4 0x39c 0x508 0x12 0x002

#define MX25_PAD_SD1_DATA3__GPIO_2_28		0x1a4 0x39c 0x000 0x15 0x000



#define MX25_PAD_KPP_ROW0__KPP_ROW0		0x1a8 0x3a0 0x000 0x10 0x000

#define MX25_PAD_KPP_ROW0__UART1_DTR		0x1a8 0x3a0 0x000 0x14 0x000

#define MX25_PAD_KPP_ROW0__GPIO_2_29		0x1a8 0x3a0 0x000 0x15 0x000

#define MX25_PAD_KPP_ROW0__KPP_ROW0		0x1a8 0x3a0 0x000 0x00 0x000

#define MX25_PAD_KPP_ROW0__UART3_RXD		0x1a8 0x3a0 0x568 0x01 0x001

#define MX25_PAD_KPP_ROW0__UART1_DTR		0x1a8 0x3a0 0x000 0x04 0x000

#define MX25_PAD_KPP_ROW0__GPIO_2_29		0x1a8 0x3a0 0x000 0x05 0x000



#define MX25_PAD_KPP_ROW1__KPP_ROW1		0x1ac 0x3a4 0x000 0x10 0x000

#define MX25_PAD_KPP_ROW1__GPIO_2_30		0x1ac 0x3a4 0x000 0x15 0x000

#define MX25_PAD_KPP_ROW1__KPP_ROW1		0x1ac 0x3a4 0x000 0x00 0x000

#define MX25_PAD_KPP_ROW1__UART3_TXD		0x1ac 0x3a4 0x000 0x01 0x000

#define MX25_PAD_KPP_ROW1__UART1_DSR		0x1ac 0x3a4 0x000 0x04 0x000

#define MX25_PAD_KPP_ROW1__GPIO_2_30		0x1ac 0x3a4 0x000 0x05 0x000



#define MX25_PAD_KPP_ROW2__KPP_ROW2		0x1b0 0x3a8 0x000 0x10 0x000

#define MX25_PAD_KPP_ROW2__CSI_D0		0x1b0 0x3a8 0x488 0x13 0x002

#define MX25_PAD_KPP_ROW2__UART1_DCD		0x1b0 0x3a8 0x000 0x14 0x000

#define MX25_PAD_KPP_ROW2__GPIO_2_31		0x1b0 0x3a8 0x000 0x15 0x000

#define MX25_PAD_KPP_ROW2__KPP_ROW2		0x1b0 0x3a8 0x000 0x00 0x000

#define MX25_PAD_KPP_ROW2__UART3_RTS		0x1b0 0x3a8 0x000 0x01 0x000

#define MX25_PAD_KPP_ROW2__CSI_D0		0x1b0 0x3a8 0x488 0x03 0x002

#define MX25_PAD_KPP_ROW2__UART1_DCD		0x1b0 0x3a8 0x000 0x04 0x000

#define MX25_PAD_KPP_ROW2__GPIO_2_31		0x1b0 0x3a8 0x000 0x05 0x000



#define MX25_PAD_KPP_ROW3__KPP_ROW3		0x1b4 0x3ac 0x000 0x10 0x000

#define MX25_PAD_KPP_ROW3__CSI_D1		0x1b4 0x3ac 0x48c 0x13 0x002

#define MX25_PAD_KPP_ROW3__GPIO_3_0		0x1b4 0x3ac 0x000 0x15 0x000

#define MX25_PAD_KPP_ROW3__KPP_ROW3		0x1b4 0x3ac 0x000 0x00 0x000

#define MX25_PAD_KPP_ROW3__UART3_CTS		0x1b4 0x3ac 0x000 0x01 0x000

#define MX25_PAD_KPP_ROW3__CSI_D1		0x1b4 0x3ac 0x48c 0x03 0x002

#define MX25_PAD_KPP_ROW3__UART1_RI		0x1b4 0x3ac 0x000 0x04 0x000

#define MX25_PAD_KPP_ROW3__GPIO_3_0		0x1b4 0x3ac 0x000 0x05 0x000



#define MX25_PAD_KPP_COL0__KPP_COL0		0x1b8 0x3b0 0x000 0x10 0x000

#define MX25_PAD_KPP_COL0__UART4_RXD_MUX	0x1b8 0x3b0 0x570 0x11 0x001

#define MX25_PAD_KPP_COL0__UART4_RXD		0x1b8 0x3b0 0x570 0x11 0x001

#define MX25_PAD_KPP_COL0__AUD5_TXD		0x1b8 0x3b0 0x000 0x12 0x000

#define MX25_PAD_KPP_COL0__GPIO_3_1		0x1b8 0x3b0 0x000 0x15 0x000



#define MX25_PAD_KPP_COL1__KPP_COL1		0x1bc 0x3b4 0x000 0x10 0x000

#define MX25_PAD_KPP_COL1__UART4_TXD_MUX	0x1bc 0x3b4 0x000 0x11 0x000

#define MX25_PAD_KPP_COL1__UART4_TXD		0x1bc 0x3b4 0x000 0x11 0x000

#define MX25_PAD_KPP_COL1__AUD5_RXD		0x1bc 0x3b4 0x000 0x12 0x000

#define MX25_PAD_KPP_COL1__GPIO_3_2		0x1bc 0x3b4 0x000 0x15 0x000



#define MX25_PAD_KPP_COL2__KPP_COL2		0x1c0 0x3b8 0x000 0x10 0x000

#define MX25_PAD_KPP_COL2__UART4_RTS		0x1c0 0x3b8 0x000 0x11 0x000

#define MX25_PAD_KPP_COL2__AUD5_TXC		0x1c0 0x3b8 0x000 0x12 0x000

#define MX25_PAD_KPP_COL2__GPIO_3_3		0x1c0 0x3b8 0x000 0x15 0x000

#define MX25_PAD_KPP_COL2__KPP_COL2		0x1c0 0x3b8 0x000 0x00 0x000

#define MX25_PAD_KPP_COL2__UART4_RTS		0x1c0 0x3b8 0x56c 0x01 0x001

#define MX25_PAD_KPP_COL2__AUD5_TXC		0x1c0 0x3b8 0x000 0x02 0x000

#define MX25_PAD_KPP_COL2__GPIO_3_3		0x1c0 0x3b8 0x000 0x05 0x000



#define MX25_PAD_KPP_COL3__KPP_COL3		0x1c4 0x3bc 0x000 0x10 0x000

#define MX25_PAD_KPP_COL3__UART4_CTS		0x1c4 0x3bc 0x000 0x11 0x000
@@ -557,9 +571,10 @@ 
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	0x210 0x000 0x000 0x10 0x000

#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16		0x210 0x000 0x000 0x15 0x000



#define MX25_PAD_VSTBY_REQ__VSTBY_REQ		0x214 0x408 0x000 0x10 0x000

#define MX25_PAD_VSTBY_REQ__AUD7_TXFS		0x214 0x408 0x000 0x14 0x000

#define MX25_PAD_VSTBY_REQ__GPIO_3_17		0x214 0x408 0x000 0x15 0x000

#define MX25_PAD_VSTBY_REQ__VSTBY_REQ		0x214 0x408 0x000 0x00 0x000

#define MX25_PAD_VSTBY_REQ__AUD7_TXFS		0x214 0x408 0x000 0x04 0x000

#define MX25_PAD_VSTBY_REQ__GPIO_3_17		0x214 0x408 0x000 0x05 0x000

#define MX25_PAD_VSTBY_REQ__UART4_RTS		0x214 0x408 0x56c 0x06 0x002



#define MX25_PAD_VSTBY_ACK__VSTBY_ACK		0x218 0x40c 0x000 0x10 0x000

#define MX25_PAD_VSTBY_ACK__GPIO_3_18		0x218 0x40c 0x000 0x15 0x000
@@ -567,6 +582,7 @@ 
#define MX25_PAD_POWER_FAIL__POWER_FAIL		0x21c 0x410 0x000 0x10 0x000

#define MX25_PAD_POWER_FAIL__AUD7_RXD		0x21c 0x410 0x478 0x14 0x001

#define MX25_PAD_POWER_FAIL__GPIO_3_19		0x21c 0x410 0x000 0x15 0x000

#define MX25_PAD_POWER_FAIL__UART4_CTS		0x21c 0x410 0x000 0x16 0x000



#define MX25_PAD_CLKO__CLKO			0x220 0x414 0x000 0x10 0x000

#define MX25_PAD_CLKO__GPIO_2_21		0x220 0x414 0x000 0x15 0x000

arch/arm/boot/dts/imx28.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -434,6 +434,32 @@ 
					fsl,pull-up = <MXS_PULL_ENABLE>;

				};



				mac0_pins_b: mac0@1 {

					reg = <1>;

					fsl,pinmux-ids = <

						MX28_PAD_ENET0_MDC__ENET0_MDC

						MX28_PAD_ENET0_MDIO__ENET0_MDIO

						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN

						MX28_PAD_ENET0_RXD0__ENET0_RXD0

						MX28_PAD_ENET0_RXD1__ENET0_RXD1

						MX28_PAD_ENET0_RXD2__ENET0_RXD2

						MX28_PAD_ENET0_RXD3__ENET0_RXD3

						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN

						MX28_PAD_ENET0_TXD0__ENET0_TXD0

						MX28_PAD_ENET0_TXD1__ENET0_TXD1

						MX28_PAD_ENET0_TXD2__ENET0_TXD2

						MX28_PAD_ENET0_TXD3__ENET0_TXD3

						MX28_PAD_ENET_CLK__CLKCTRL_ENET

						MX28_PAD_ENET0_COL__ENET0_COL

						MX28_PAD_ENET0_CRS__ENET0_CRS

						MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK

						MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK

						>;

					fsl,drive-strength = <MXS_DRIVE_8mA>;

					fsl,voltage = <MXS_VOLTAGE_HIGH>;

					fsl,pull-up = <MXS_PULL_ENABLE>;

				};



				mac1_pins_a: mac1@0 {

					reg = <0>;

					fsl,pinmux-ids = <

arch/arm/boot/dts/imx31.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -69,6 +69,14 @@ 
				status = "disabled";

			};



			kpp: kpp@43fa8000 {

				compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";

				reg = <0x43fa8000 0x4000>;

				interrupts = <24>;

				clocks = <&clks 46>;

				status = "disabled";

			};



			uart4: serial@43fb0000 {

				compatible = "fsl,imx31-uart", "fsl,imx21-uart";

				reg = <0x43fb0000 0x4000>;