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Commit 40e8550a authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm: Move WIMG update to helper. 



Only difference here is, we apply the WIMG mapping early, so rflags
passed to updatepp will also be changed.

Acked-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent c6a3c495

arch/powerpc/mm/hash64_4k.c

+0 −5
Original line number Diff line number Diff line
@@ -54,11 +54,6 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid, 
	 * need to add in 0x1 if it's a read-only user page

	 */

	rflags = htab_convert_pte_flags(new_pte);

	/*

	 * Add in WIMG bits

	 */

	rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |

				_PAGE_COHERENT | _PAGE_GUARDED));



	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&

	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))

arch/powerpc/mm/hash64_64k.c

+0 −10
Original line number Diff line number Diff line
@@ -86,11 +86,6 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid, 
	 */

	subpg_pte = new_pte & ~subpg_prot;

	rflags = htab_convert_pte_flags(subpg_pte);

	/*

	 * Add in WIMG bits

	 */

	rflags |= (subpg_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |

				_PAGE_COHERENT | _PAGE_GUARDED));



	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&

	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
@@ -258,11 +253,6 @@ int __hash_page_64K(unsigned long ea, unsigned long access, 
					  old_pte, new_pte));



	rflags = htab_convert_pte_flags(new_pte);

	/*

	 * Add in WIMG bits

	 */

	rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |

				_PAGE_COHERENT | _PAGE_GUARDED));



	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&

	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))

arch/powerpc/mm/hash_utils_64.c

+12 −1
Original line number Diff line number Diff line
@@ -182,7 +182,18 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) 
	/*

	 * Always add "C" bit for perf. Memory coherence is always enabled

	 */

	return rflags | HPTE_R_C | HPTE_R_M;

	rflags |=  HPTE_R_C | HPTE_R_M;

	/*

	 * Add in WIG bits

	 */

	if (pteflags & _PAGE_WRITETHRU)

		rflags |= HPTE_R_W;

	if (pteflags & _PAGE_NO_CACHE)

		rflags |= HPTE_R_I;

	if (pteflags & _PAGE_GUARDED)

		rflags |= HPTE_R_G;



	return rflags;

}



int htab_bolt_mapping(unsigned long vstart, unsigned long vend,

arch/powerpc/mm/hugepage-hash64.c

+0 −7
Original line number Diff line number Diff line
@@ -120,13 +120,6 @@ int __hash_page_thp(unsigned long ea, unsigned long access, unsigned long vsid, 
		pa = pmd_pfn(__pmd(old_pmd)) << PAGE_SHIFT;

		new_pmd |= _PAGE_HASHPTE;



		/* Add in WIMG bits */

		rflags |= (new_pmd & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |

				      _PAGE_GUARDED));

		/*

		 * enable the memory coherence always

		 */

		rflags |= HPTE_R_M;

repeat:

		hpte_group = ((hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;

arch/powerpc/mm/hugetlbpage-hash64.c

+0 −8
Original line number Diff line number Diff line
@@ -91,14 +91,6 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, 
		/* clear HPTE slot informations in new PTE */

		new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;



		/* Add in WIMG bits */

		rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |

				      _PAGE_COHERENT | _PAGE_GUARDED));

		/*

		 * enable the memory coherence always

		 */

		rflags |= HPTE_R_M;



		slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,

					     mmu_psize, ssize);