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Commit 40ceda09 authored by yong mao's avatar yong mao Committed by Ulf Hansson
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mmc: mediatek: Fixed bug where clock frequency could be set wrong 



This patch can fix two issues:

Issue 1:
In previous code, div may be overflow when setting clock frequency
as f_min. We can use DIV_ROUND_UP to fix this boundary related
issue.

Issue 2:
In previous code, we can not set the correct clock frequency when
div equals 0xff.

Signed-off-by: default avatarYong Mao <yong.mao@mediatek.com>
Signed-off-by: default avatarChaotian Jing <chaotian.jing@mediatek.com>
Reviewed-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 8ecc3444

drivers/mmc/host/mtk-sd.c

+2 −2
Original line number Diff line number Diff line
@@ -580,7 +580,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 
		}

	}

	sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,

			(mode << 8) | (div % 0xff));

		      (mode << 8) | div);

	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);

	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))

		cpu_relax();
@@ -1559,7 +1559,7 @@ static int msdc_drv_probe(struct platform_device *pdev) 
	host->src_clk_freq = clk_get_rate(host->src_clk);

	/* Set host parameters to mmc */

	mmc->ops = &mt_msdc_ops;

	mmc->f_min = host->src_clk_freq / (4 * 255);

	mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);



	mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;

	/* MMC core transfer sizes tunable parameters */