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Commit 40906354 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo
Browse files

ARM i.MX51: Add Digi ConnectCore devicetree 



This patch adds support for Digi ConnectCore® i.MX51/Wi-i.MX51 SOM
and basic support for the ConnectCore for i.MX51 JumpStart Kit.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 3c3ea296

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -162,6 +162,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ 
	imx51-apf51.dtb \

	imx51-apf51dev.dtb \

	imx51-babbage.dtb \

	imx51-digi-connectcore-jsk.dtb \

	imx51-eukrea-mbimxsd51-baseboard.dtb \

	imx53-ard.dtb \

	imx53-m53evk.dtb \

arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts

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+108 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



#include "imx51-digi-connectcore-som.dtsi"



/ {

	model = "Digi ConnectCore CC(W)-MX51 JSK";

	compatible = "digi,connectcore-ccxmx51-jsk",

		     "digi,connectcore-ccxmx51-som", "fsl,imx51";



	chosen {

		linux,stdout-path = &uart1;

	};

};



&owire {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_owire>;

	status = "okay";

};



&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;

	status = "okay";

};



&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

	status = "okay";

};



&uart3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart3>;

	status = "okay";

};



&usbotg {

	dr_mode = "otg";

	status = "okay";

};



&usbh1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usbh1>;

	dr_mode = "host";

	phy_type = "ulpi";

	disable-over-current;

	status = "okay";

};



&iomuxc {

	imx51-digi-connectcore-jsk {

		pinctrl_owire: owiregrp {

			fsl,pins = <

				MX51_PAD_OWIRE_LINE__OWIRE_LINE		0x40000000

			>;

		};



		pinctrl_uart1: uart1grp {

			fsl,pins = <

				MX51_PAD_UART1_RXD__UART1_RXD		0x1c5

				MX51_PAD_UART1_TXD__UART1_TXD		0x1c5

			>;

		};



		pinctrl_uart2: uart2grp {

			fsl,pins = <

				MX51_PAD_UART2_RXD__UART2_RXD		0x1c5

				MX51_PAD_UART2_TXD__UART2_TXD		0x1c5

			>;

		};



		pinctrl_uart3: uart3grp {

			fsl,pins = <

				MX51_PAD_UART3_RXD__UART3_RXD		0x1c5

				MX51_PAD_UART3_TXD__UART3_TXD		0x1c5

			>;

		};



		pinctrl_usbh1: usbh1grp {

			fsl,pins = <

				MX51_PAD_USBH1_DATA0__USBH1_DATA0	0x1e5

				MX51_PAD_USBH1_DATA1__USBH1_DATA1	0x1e5

				MX51_PAD_USBH1_DATA2__USBH1_DATA2	0x1e5

				MX51_PAD_USBH1_DATA3__USBH1_DATA3	0x1e5

				MX51_PAD_USBH1_DATA4__USBH1_DATA4	0x1e5

				MX51_PAD_USBH1_DATA5__USBH1_DATA5	0x1e5

				MX51_PAD_USBH1_DATA6__USBH1_DATA6	0x1e5

				MX51_PAD_USBH1_DATA7__USBH1_DATA7	0x1e5

				MX51_PAD_USBH1_CLK__USBH1_CLK		0x1e5

				MX51_PAD_USBH1_DIR__USBH1_DIR		0x1e5

				MX51_PAD_USBH1_NXT__USBH1_NXT		0x1e5

				MX51_PAD_USBH1_STP__USBH1_STP		0x1e5

			>;

		};

	};

};

arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi

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Original line number Diff line number Diff line 
/*

 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/dts-v1/;

#include "imx51.dtsi"



/ {

	model = "Digi ConnectCore CC(W)-MX51";

	compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";



	memory {

		reg = <0x90000000 0x08000000>;

	};

};



&ecspi1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi1>;

	fsl,spi-num-chipselects = <1>;

	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;

	status = "okay";



	pmic: mc13892@0 {

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_mc13892>;

		compatible = "fsl,mc13892";

		spi-max-frequency = <16000000>;

		spi-cs-high;

		reg = <0>;

		interrupt-parent = <&gpio1>;

		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

		fsl,mc13xxx-uses-rtc;



		regulators {

			sw1_reg: sw1 {

				regulator-min-microvolt = <1000000>;

				regulator-max-microvolt = <1100000>;

				regulator-boot-on;

				regulator-always-on;

			};



			sw2_reg: sw2 {

				regulator-min-microvolt = <1225000>;

				regulator-max-microvolt = <1225000>;

				regulator-boot-on;

				regulator-always-on;

			};



			sw3_reg: sw3 {

				regulator-min-microvolt = <1200000>;

				regulator-max-microvolt = <1200000>;

				regulator-boot-on;

				regulator-always-on;

			};



			swbst_reg: swbst { };



			viohi_reg: viohi {

				regulator-always-on;

			};



			vpll_reg: vpll {

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

			};



			vdig_reg: vdig {

				regulator-min-microvolt = <1250000>;

				regulator-max-microvolt = <1250000>;

				regulator-always-on;

			};



			vsd_reg: vsd {

				regulator-min-microvolt = <3150000>;

				regulator-max-microvolt = <3150000>;

				regulator-always-on;

			};



			vusb2_reg: vusb2 {

				regulator-min-microvolt = <2600000>;

				regulator-max-microvolt = <2600000>;

				regulator-always-on;

			};



			vvideo_reg: vvideo {

				regulator-min-microvolt = <2775000>;

				regulator-max-microvolt = <2775000>;

				regulator-always-on;

			};



			vaudio_reg: vaudio {

				regulator-min-microvolt = <3000000>;

				regulator-max-microvolt = <3000000>;

				regulator-always-on;

			};



			vcam_reg: vcam {

				regulator-min-microvolt = <2750000>;

				regulator-max-microvolt = <2750000>;

				regulator-always-on;

			};



			vgen1_reg: vgen1 {

				regulator-min-microvolt = <1200000>;

				regulator-max-microvolt = <1200000>;

				regulator-always-on;

			};



			vgen2_reg: vgen2 {

				regulator-min-microvolt = <3150000>;

				regulator-max-microvolt = <3150000>;

				regulator-always-on;

			};



			vgen3_reg: vgen3 {

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

			};



			vusb_reg: vusb {

				regulator-always-on;

			};



			gpo1_reg: gpo1 { };



			gpo2_reg: gpo2 { };



			gpo3_reg: gpo3 { };



			gpo4_reg: gpo4 { };



			pwgt2spi_reg: pwgt2spi {

				regulator-always-on;

			};



			vcoincell_reg: vcoincell {

				regulator-min-microvolt = <3000000>;

				regulator-max-microvolt = <3000000>;

				regulator-always-on;

			};

		};

	};

};



&esdhc2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_esdhc2>;

	cap-sdio-irq;

	enable-sdio-wakeup;

	keep-power-in-suspend;

	max-frequency = <50000000>;

	no-1-8-v;

	non-removable;

	vmmc-supply = <&gpo4_reg>;

	status = "okay";

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec>;

	phy-mode = "mii";

	phy-supply = <&gpo3_reg>;

	/* Pins shared with LCD2, keep status disabled */

};



&i2c2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c2>;

	clock-frequency = <400000>;

	status = "okay";



	mma7455l@1d {

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_mma7455l>;

		compatible = "fsl,mma7455l";

		reg = <0x1d>;

		interrupt-parent = <&gpio1>;

		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;

	};

};



&nfc {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_nfc>;

	nand-bus-width = <8>;

	nand-ecc-mode = "hw";

	nand-on-flash-bbt;

	#address-cells = <1>;

	#size-cells = <1>;

	status = "okay";

};



&usbotg {

	phy_type = "utmi_wide";

	disable-over-current;

	/* Device role is not known, keep status disabled */

};



&weim {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_weim>;

	status = "okay";



	lan9221: lan9221@5,0 {

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_lan9221>;

		compatible = "smsc,lan9221", "smsc,lan9115";

		reg = <5 0x00000000 0x1000>;

		fsl,weim-cs-timing = <

			0x00420081 0x00000000

			0x32260000 0x00000000

			0x72080f00 0x00000000

		>;

		clocks = <&clks IMX5_CLK_DUMMY>;

		interrupt-parent = <&gpio1>;

		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;

		phy-mode = "mii";

		reg-io-width = <2>;

		smsc,irq-push-pull;

		vdd33a-supply = <&gpo2_reg>;

		vddvario-supply = <&gpo2_reg>;

	};

};



&iomuxc {

	imx51-digi-connectcore-som {

		pinctrl_ecspi1: ecspi1grp {

			fsl,pins = <

				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185

				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185

				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185

				MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */

			>;

		};



		pinctrl_esdhc2: esdhc2grp {

			fsl,pins = <

				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5

				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5

				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5

				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5

				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5

				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5

			>;

		};



		pinctrl_fec: fecgrp {

			fsl,pins = <

				MX51_PAD_DI_GP3__FEC_TX_ER		0x80000000

				MX51_PAD_DI2_PIN4__FEC_CRS		0x80000000

				MX51_PAD_DI2_PIN2__FEC_MDC		0x80000000

				MX51_PAD_DI2_PIN3__FEC_MDIO		0x80000000

				MX51_PAD_DI2_DISP_CLK__FEC_RDATA1	0x80000000

				MX51_PAD_DI_GP4__FEC_RDATA2		0x80000000

				MX51_PAD_DISP2_DAT0__FEC_RDATA3		0x80000000

				MX51_PAD_DISP2_DAT1__FEC_RX_ER		0x80000000

				MX51_PAD_DISP2_DAT6__FEC_TDATA1		0x80000000

				MX51_PAD_DISP2_DAT7__FEC_TDATA2		0x80000000

				MX51_PAD_DISP2_DAT8__FEC_TDATA3		0x80000000

				MX51_PAD_DISP2_DAT9__FEC_TX_EN		0x80000000

				MX51_PAD_DISP2_DAT10__FEC_COL		0x80000000

				MX51_PAD_DISP2_DAT11__FEC_RX_CLK	0x80000000

				MX51_PAD_DISP2_DAT12__FEC_RX_DV		0x80000000

				MX51_PAD_DISP2_DAT13__FEC_TX_CLK	0x80000000

				MX51_PAD_DISP2_DAT14__FEC_RDATA0	0x80000000

				MX51_PAD_DISP2_DAT15__FEC_TDATA0	0x80000000

			>;

		};



		pinctrl_i2c2: i2c2grp {

			fsl,pins = <

				MX51_PAD_GPIO1_2__I2C2_SCL		0x400001ed

				MX51_PAD_GPIO1_3__I2C2_SDA		0x400001ed

			>;

		};



		pinctrl_nfc: nfcgrp {

			fsl,pins = <

				MX51_PAD_NANDF_D0__NANDF_D0		0x80000000

				MX51_PAD_NANDF_D1__NANDF_D1		0x80000000

				MX51_PAD_NANDF_D2__NANDF_D2		0x80000000

				MX51_PAD_NANDF_D3__NANDF_D3		0x80000000

				MX51_PAD_NANDF_D4__NANDF_D4		0x80000000

				MX51_PAD_NANDF_D5__NANDF_D5		0x80000000

				MX51_PAD_NANDF_D6__NANDF_D6		0x80000000

				MX51_PAD_NANDF_D7__NANDF_D7		0x80000000

				MX51_PAD_NANDF_ALE__NANDF_ALE		0x80000000

				MX51_PAD_NANDF_CLE__NANDF_CLE		0x80000000

				MX51_PAD_NANDF_RE_B__NANDF_RE_B		0x80000000

				MX51_PAD_NANDF_WE_B__NANDF_WE_B		0x80000000

				MX51_PAD_NANDF_WP_B__NANDF_WP_B		0x80000000

				MX51_PAD_NANDF_CS0__NANDF_CS0		0x80000000

				MX51_PAD_NANDF_RB0__NANDF_RB0		0x80000000

			>;

		};



		pinctrl_lan9221: lan9221grp {

			fsl,pins = <

				MX51_PAD_GPIO1_9__GPIO1_9		0xe5 /* IRQ */

			>;

		};



		pinctrl_mc13892: mc13892grp {

			fsl,pins = <

				MX51_PAD_GPIO1_5__GPIO1_5		0xe5 /* IRQ */

			>;

		};



		pinctrl_mma7455l: mma7455lgrp {

			fsl,pins = <

				MX51_PAD_GPIO1_7__GPIO1_7		0xe5 /* IRQ1 */

				MX51_PAD_GPIO1_6__GPIO1_6		0xe5 /* IRQ2 */

			>;

		};



		pinctrl_weim: weimgrp {

			fsl,pins = <

				MX51_PAD_EIM_DA0__EIM_DA0		0x80000000

				MX51_PAD_EIM_DA1__EIM_DA1		0x80000000

				MX51_PAD_EIM_DA2__EIM_DA2		0x80000000

				MX51_PAD_EIM_DA3__EIM_DA3		0x80000000

				MX51_PAD_EIM_DA4__EIM_DA4		0x80000000

				MX51_PAD_EIM_DA5__EIM_DA5		0x80000000

				MX51_PAD_EIM_DA6__EIM_DA6		0x80000000

				MX51_PAD_EIM_DA7__EIM_DA7		0x80000000

				MX51_PAD_EIM_DA8__EIM_DA8		0x80000000

				MX51_PAD_EIM_DA9__EIM_DA9		0x80000000

				MX51_PAD_EIM_DA10__EIM_DA10		0x80000000

				MX51_PAD_EIM_DA11__EIM_DA11		0x80000000

				MX51_PAD_EIM_DA12__EIM_DA12		0x80000000

				MX51_PAD_EIM_DA13__EIM_DA13		0x80000000

				MX51_PAD_EIM_DA14__EIM_DA14		0x80000000

				MX51_PAD_EIM_DA15__EIM_DA15		0x80000000

				MX51_PAD_EIM_A16__EIM_A16		0x80000000

				MX51_PAD_EIM_A17__EIM_A17		0x80000000

				MX51_PAD_EIM_A18__EIM_A18		0x80000000

				MX51_PAD_EIM_A19__EIM_A19		0x80000000

				MX51_PAD_EIM_A20__EIM_A20		0x80000000

				MX51_PAD_EIM_A21__EIM_A21		0x80000000

				MX51_PAD_EIM_A22__EIM_A22		0x80000000

				MX51_PAD_EIM_A23__EIM_A23		0x80000000

				MX51_PAD_EIM_A24__EIM_A24		0x80000000

				MX51_PAD_EIM_A25__EIM_A25		0x80000000

				MX51_PAD_EIM_A26__EIM_A26		0x80000000

				MX51_PAD_EIM_A27__EIM_A27		0x80000000

				MX51_PAD_EIM_D16__EIM_D16		0x80000000

				MX51_PAD_EIM_D17__EIM_D17		0x80000000

				MX51_PAD_EIM_D18__EIM_D18		0x80000000

				MX51_PAD_EIM_D19__EIM_D19		0x80000000

				MX51_PAD_EIM_D20__EIM_D20		0x80000000

				MX51_PAD_EIM_D21__EIM_D21		0x80000000

				MX51_PAD_EIM_D22__EIM_D22		0x80000000

				MX51_PAD_EIM_D23__EIM_D23		0x80000000

				MX51_PAD_EIM_D24__EIM_D24		0x80000000

				MX51_PAD_EIM_D25__EIM_D25		0x80000000

				MX51_PAD_EIM_D26__EIM_D26		0x80000000

				MX51_PAD_EIM_D27__EIM_D27		0x80000000

				MX51_PAD_EIM_D28__EIM_D28		0x80000000

				MX51_PAD_EIM_D29__EIM_D29		0x80000000

				MX51_PAD_EIM_D30__EIM_D30		0x80000000

				MX51_PAD_EIM_D31__EIM_D31		0x80000000

				MX51_PAD_EIM_OE__EIM_OE			0x80000000

				MX51_PAD_EIM_DTACK__EIM_DTACK		0x80000000

				MX51_PAD_EIM_LBA__EIM_LBA		0x80000000

				MX51_PAD_EIM_CS5__EIM_CS5		0x80000000 /* CS5 */

			>;

		};

	};

};