Loading include/asm-blackfin/mach-bf548/cdefBF54x_base.h +0 −33 Original line number Diff line number Diff line Loading @@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) #define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) #define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val) #define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) #define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) #define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) #define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) #define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL) #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val) #define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) #define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) #define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) #define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) #define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL) #define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val) #define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) #define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) #define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) #define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) #define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ Loading Loading
include/asm-blackfin/mach-bf548/cdefBF54x_base.h +0 −33 Original line number Diff line number Diff line Loading @@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) #define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) #define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val) #define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) #define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) #define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) #define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) #define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL) #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val) #define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) #define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) #define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) #define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) #define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL) #define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val) #define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) #define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) #define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) #define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) #define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ /* SPORT1 Registers */ Loading
Bryan Wu <bryan.wu@analog.com>Bryan Wu <bryan.wu@analog.com>