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Commit 404a6a51 authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher
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drm/radeon: Only flush HDP cache from idle ioctl if BO is in VRAM 



The HDP cache only applies to CPU access to VRAM.

Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6b57f20c

drivers/gpu/drm/radeon/radeon_gem.c

+4 −2
Original line number Diff line number Diff line
@@ -358,15 +358,17 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 
	struct drm_gem_object *gobj;

	struct radeon_bo *robj;

	int r;

	uint32_t cur_placement = 0;



	gobj = drm_gem_object_lookup(dev, filp, args->handle);

	if (gobj == NULL) {

		return -ENOENT;

	}

	robj = gem_to_radeon_bo(gobj);

	r = radeon_bo_wait(robj, NULL, false);

	r = radeon_bo_wait(robj, &cur_placement, false);

	/* Flush HDP cache via MMIO if necessary */

	if (rdev->asic->mmio_hdp_flush)

	if (rdev->asic->mmio_hdp_flush &&

	    radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)

		robj->rdev->asic->mmio_hdp_flush(rdev);

	drm_gem_object_unreference_unlocked(gobj);

	r = radeon_gem_handle_lockup(rdev, r);