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Commit 402bc06e authored by Prerna Kalla's avatar Prerna Kalla
Browse files

ARM: dts: msm: Add inline crypto emmc node for lagoon 

Add Inline Crypto Engine device node and crypto support
for Embedded MultiMediaCard storage, to support File
Based Encryption.

Change-Id: I993aef26b44672c99d570f7d2ae741bb752cf991
parent 96e5bad9

qcom/lagoon.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -2498,6 +2498,32 @@ 
		};

	};



	sdcc1_ice: sdcc1ice@7c8000 {

		compatible = "qcom,ice";

		reg = <0x7c8000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,

			<&gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&gcc GCC_SDCC1_AHB_CLK>,

			<&gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_UFS_MEM_CFG 0 0>,

				 /* No vote */

				<MSM_BUS_MASTER_AMPSS_M0

				 MSM_BUS_SLAVE_UFS_MEM_CFG 1000 0>;

				 /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	sdhc_1: sdhci@7c4000 {

		compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";

		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>;
@@ -2506,6 +2532,7 @@ 
		interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,

				 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;