iommu/arm-smmu: Merge of smmu changes from 4.14 to msm-kona

subsystem that the buffer is fully accessible at the elevated privilege

level (and ideally inaccessible or at least read-only at the

lesser-privileged levels).

DMA_ATTR_IOMMU_USE_LLC_NWA

------------------------------------

DMA_ATTR_IOMMU_USE_LLC_NWA: Overrides the bus attributes to use

System Cache(LLC) with allocation policy as Inner Non-Cacheable, Outer Cacheable:

Write-Back, Read-Allocate, No Write-Allocate policy.

                        "arm,mmu-401"

                        "arm,mmu-500"

                        "cavium,smmu-v2"

                        "qcom,smmu-v2"

                        "qcom,qsmmu-v500"

                  depending on the particular implementation and/or the

                  version of the architecture implemented.

- reg           : Base address and size of the SMMU.

- reg-names	: For the "qcom,qsmmu-v500" device "tcu-base" is expected.

- #global-interrupts : The number of global interrupts exposed by the

                       device.

                  property is not valid for SMMUs using stream indexing,

                  or using stream matching with #iommu-cells = <2>, and

                  may be ignored if present in such cases.

- attach-impl-defs : global registers to program at device attach

                  time. This should be a list of 2-tuples of the format:

                  <offset reg_value>.

- qcom,fatal-asf : Enable BUG_ON for address size faults.  Some hardware

                  requires special fixups to recover from address size

                  faults.  Rather than applying the fixups just BUG since

                  address size faults are due to a fundamental programming

                  error from which we don't care about recovering anyways.

- qcom,tz-device-id : A string indicating the device ID for this SMMU known

		  to TZ.  See msm_tz_smmu.c for a full list of mappings.

- qcom,skip-init : Disable resetting configuration for all context banks

                  during device reset.  This is useful for targets where

                  some context banks are dedicated to other execution

                  environments outside of Linux and those other EEs are

                  programming their own stream match tables, SCTLR, etc.

                  Without setting this option we will trample on their

                  configuration.

- qcom,dynamic  : Allow dynamic domains to be attached. This is only

		  useful if the upstream hardware is capable of switching

		  between multiple domains within a single context bank.

- qcom,use-3-lvl-tables:

		  Some hardware configurations may not be optimized for using

		  a four level page table configuration. Set to use a three

		  level page table instead.

- qcom,no-asid-retention:

		  Some hardware may lose internal state for asid after

		  retention. No cache invalidation operations involving asid

		  may be used.

- qcom,actlr:

		  An array of <sid mask actlr-setting>.

		  Any sid X for which X&~mask==sid will be programmed with the

		  given actlr-setting.

- qcom,enable-static-cb : Enables option to use pre-defined static context bank

		  allocation programmed by TZ. Global register including SMR and

		  S2CR registers are configured by TZ before kernel comes up and

		  this programming is not altered throughout the life of system.

		  We would be reading through these registers at run time to

		  identify CB allocated for a particular sid. SID masking isn't

		  supported as we are directly comparing client SID with ID bits

		  of SMR registers.

-qcom,disable-atos:

		  Some hardware may not have full support for atos debugging

		  in tandem with other features like power collapse.

- qcom,deferred-regulator-disable-delay : The time delay for deferred regulator

                  disable in ms. In case of unmap call, regulator is

                  enabled/disabled. This may introduce additional delay. For

                  clients who do not detach, it's not possible to keep regulator

                  vote while smmu is attached. Type is <u32>.

- clocks        : List of clocks to be used during SMMU register access. See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for information about the format. For each clock specified

                  here, there must be a corresponding entry in clock-names

                  (see below).

- clock-names   : List of clock names corresponding to the clocks specified in

                  the "clocks" property (above). See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for more info.

- (%s)-supply   : Phandle of the regulator that should be powered on during

                  SMMU register access. (%s) is a string from the

		  qcom,regulator-names property.

- qcom,regulator-names :

		  List of strings to use with the (%s)-supply property.

- qcom,msm-bus,name

- qcom,msm-bus,num-cases

- qcom,msm-bus,num-paths

- qcom,msm-bus,vectors-KBps

		: Refer to devicetree/bindings/arm/msm/msm_bus.txt

** Deprecated properties:

        };

        /* ARM MMU-500 with 10-bit stream ID input configuration */

        smmu3: iommu {

                compatible = "arm,mmu-500", "arm,smmu-v2";

                ...

                #iommu-cells = <1>;

                /* always ignore appended 5-bit TBU number */

                stream-match-mask = 0x7c00;

        };

* Qualcomm MMU-500 TBU Device

        bus {

                /* bus whose child devices emit one unique 10-bit stream

                   ID each, but may master through multiple SMMU TBUs */

                iommu-map = <0 &smmu3 0 0x400>;

                ...

The qcom,qsmmu-v500 device implements a number of register regions containing

debug functionality. Each register region maps to a separate tbu from the

arm mmu-500 implementation.

** TBU required properties:

- compatible    : Should be one of:

                        "qcom,qsmmuv500-tbu"

- reg           : Base address and size.

- reg-names	: "base" and "status-reg" are expected

		"base" is the main TBU register region.

		"status-reg" indicates whether hw can process a new request.

-qcom,stream-id-range:

		Pair of values describing the smallest supported stream-id

		and the size of the entire set.

Example:

smmu {

	compatible = "qcom,qsmmu-v500";

	tbu@0x1000 {

		compatible = "qcom,qsmmuv500-tbu";

		regs = <0x1000 0x1000>,

			<0x2000 0x8>;

		reg-names = "base",

			"status-reg";

		qcom,stream-id-range = <0x800 0x400>;

	};

};

This document describes the device tree binding for IOMMU test devices.

The iommu-debug framework can optionally make use of some platform devices

for improved standalone testing and other features.

- compatible: iommu-debug-test

Required properties

===================

- iommus: The IOMMU for the test device (see iommu.txt)

Example

=======

	iommu_test_device {

		compatible = "iommu-debug-test";

		/*

		 * 42 shouldn't be used by anyone on the cpp_fd_smmu.  We just

		 * need _something_ here to get this node recognized by the

		 * SMMU driver. Our test uses ATOS, which doesn't use SIDs

		 * anyways, so using a dummy value is ok.

		 */

		iommus = <&cpp_fd_smmu 42>;

	};

source "mm/Kconfig"

config ARM64_DMA_USE_IOMMU

	bool "ARM64 DMA iommu integration"

	select ARM_HAS_SG_CHAIN

	select NEED_SG_DMA_LENGTH

	help

	  Enable using iommu through the standard dma apis.

	  dma_alloc_coherent() will allocate scatter-gather memory

	  which is made virtually contiguous via iommu.

	  Enable if system contains IOMMU hardware.

if ARM64_DMA_USE_IOMMU

config ARM64_DMA_IOMMU_ALIGNMENT

	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"

	range 4 9

	default 9

	help

	  DMA mapping framework by default aligns all buffers to the smallest

	  PAGE_SIZE order which is greater than or equal to the requested buffer

	  size. This works well for buffers up to a few hundreds kilobytes, but

	  for larger buffers it just a waste of address space. Drivers which has

	  relatively small addressing window (like 64Mib) might run out of

	  virtual space with just a few allocations.

	  With this parameter you can specify the maximum PAGE_SIZE order for

	  DMA IOMMU buffers. Larger buffers will be aligned only to this

	  specified order. The order is expressed as a power of two multiplied

	  by the PAGE_SIZE.

endif

config SECCOMP

	bool "Enable seccomp to safely compute untrusted bytecode"

	---help---

		#clock-cells = <1>;

	};

};

#include "msm-arm-smmu-kona.dtsi"