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Commit 3fdb68de authored by Tomas Winkler's avatar Tomas Winkler Committed by John W. Linville
Browse files

iwlwifi: use pci registers defined in pci_regs.h



This patch replaces where possible usage of pci register
defined in the driver by ones defined in pci_regs.h

Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent fe3d2c3f
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+0 −6
Original line number Diff line number Diff line
@@ -229,12 +229,6 @@ struct iwl3945_eeprom {

/* End of EEPROM */


#define PCI_LINK_CTRL      0x0F0
#define PCI_POWER_SOURCE   0x0C8
#define PCI_REG_WUM8       0x0E8
#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT         (0x80000000)

#define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)	/* bit 6    */
#define PCI_CFG_REV_ID_BIT_RTP                      (0x80)	/* bit 7    */

+8 −11
Original line number Diff line number Diff line
@@ -905,22 +905,18 @@ u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)

static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
{
	int rc;
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	rc = iwl_grab_nic_access(priv);
	if (rc) {
	ret = iwl_grab_nic_access(priv);
	if (ret) {
		spin_unlock_irqrestore(&priv->lock, flags);
		return rc;
		return ret;
	}

	if (src == IWL_PWR_SRC_VAUX) {
		u32 val;

		rc = pci_read_config_dword(priv->pci_dev,
				PCI_POWER_SOURCE, &val);
		if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
		if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
			iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
					APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
					~APMG_PS_CTRL_MSK_PWR_SRC);
@@ -929,8 +925,9 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
			iwl_poll_bit(priv, CSR_GPIO_IN,
				     CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
				     CSR_GPIO_IN_BIT_AUX_POWER, 5000);
		} else
		} else {
			iwl_release_nic_access(priv);
		}
	} else {
		iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
				APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
@@ -942,7 +939,7 @@ static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
	}
	spin_unlock_irqrestore(&priv->lock, flags);

	return rc;
	return ret;
}

static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
+0 −7
Original line number Diff line number Diff line
@@ -92,19 +92,12 @@
#define IWL49_RSSI_OFFSET	44



/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041
#define PCI_CFG_POWER_SOURCE	0x0C8
#define PCI_REG_WUM8		0x0E8
#define PCI_CFG_LINK_CTRL	0x0F0

/* PCI register values */
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02
#define PCI_CFG_CMD_REG_INT_DIS_MSK	0x04
#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT         (0x80000000)


#define IWL_NUM_SCAN_RATES         (2)

+13 −10
Original line number Diff line number Diff line
@@ -381,27 +381,30 @@ static int iwl4965_apm_init(struct iwl_priv *priv)
static void iwl4965_nic_config(struct iwl_priv *priv)
{
	unsigned long flags;
	u32 val;
	u16 dctl;
	u16 radio_cfg;
	u16 link;
	u16 lctl;

	spin_lock_irqsave(&priv->lock, flags);

	if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
		pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
		int pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
		pci_read_config_word(priv->pci_dev, pos + PCI_EXP_DEVCTL, &dctl);

		/* Enable No Snoop field */
		pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
				       val & ~(1 << 11));
		pci_write_config_word(priv->pci_dev, pos + PCI_EXP_DEVCTL,
					dctl & ~PCI_EXP_DEVCTL_NOSNOOP_EN);
	}

	pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
	lctl = iwl_pcie_link_ctl(priv);

	/* L1 is enabled by BIOS */
	if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
		/* disable L0S disabled L1A enabled */
	/* HW bug W/A - negligible power consumption */
	/* L1-ASPM is enabled by BIOS */
	if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
		/* L1-ASPM enabled: disable L0S  */
		iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
	else
		/* L0S enabled L1A disabled */
		/* L1-ASPM disabled: enable L0S */
		iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);

	radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
+7 −6
Original line number Diff line number Diff line
@@ -219,18 +219,19 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
{
	unsigned long flags;
	u16 radio_cfg;
	u16 link;
	u16 lctl;

	spin_lock_irqsave(&priv->lock, flags);

	pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
	lctl = iwl_pcie_link_ctl(priv);

	/* L1 is enabled by BIOS */
	if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
		/* disable L0S disabled L1A enabled */
	/* HW bug W/A */
	/* L1-ASPM is enabled by BIOS */
	if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
		/* L1-APSM enabled: disable L0S  */
		iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
	else
		/* L0S enabled L1A disabled */
		/* L1-ASPM disabled: enable L0S */
		iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);

	radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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