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Commit 3fafe9c2 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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powerpc/powernv: Add PIO accessors for Power8 LPC bus



This uses the hooks provided by CONFIG_PPC_INDIRECT_PIO to
implement a set of hooks for IO port access to use the LPC
bus via OPAL calls for the first 64K of IO space

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent b37193b7
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+8 −0
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@@ -69,6 +69,14 @@ extern unsigned long pci_dram_offset;

extern resource_size_t isa_mem_base;

/* Boolean set by platform if PIO accesses are suppored while _IO_BASE
 * is not set or addresses cannot be translated to MMIO. This is typically
 * set when the platform supports "special" PIO accesses via a non memory
 * mapped mechanism, and allows things like the early udbg UART code to
 * function.
 */
extern bool isa_io_special;

#ifdef CONFIG_PPC32
#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
+2 −0
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@@ -687,6 +687,8 @@ extern int opal_machine_check(struct pt_regs *regs);

extern void opal_shutdown(void);

extern void opal_lpc_init(void);

#endif /* __ASSEMBLY__ */

#endif /* __OPAL_H */
+3 −0
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@@ -25,6 +25,9 @@
#include <asm/firmware.h>
#include <asm/bug.h>

/* See definition in io.h */
bool isa_io_special;

void _insb(const volatile u8 __iomem *port, void *buf, long count)
{
	u8 *tbuf = buf;
+1 −0
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@@ -7,6 +7,7 @@ config PPC_POWERNV
	select PPC_P7_NAP
	select PPC_PCI_CHOICE if EMBEDDED
	select EPAPR_BOOT
	select PPC_INDIRECT_PIO
	default y

config POWERNV_MSI
+1 −1
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obj-y			+= setup.o opal-takeover.o opal-wrappers.o opal.o
obj-y			+= opal-rtc.o opal-nvram.o
obj-y			+= opal-rtc.o opal-nvram.o opal-lpc.o

obj-$(CONFIG_SMP)	+= smp.o
obj-$(CONFIG_PCI)	+= pci.o pci-p5ioc2.o pci-ioda.o
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