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Commit 3f2362c5 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I
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phy: ti-pipe3: use *syscon* framework API to set PCS value of the PHY 



Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* API to do the same.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Acked-by: default avatarRoger Quadros <rogerq@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
parent c396a1c7

Documentation/devicetree/bindings/phy/ti-phy.txt

+2 −0
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ Optional properties: 
 - syscon-pllreset: Handle to system control region that contains the

   CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0

   register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.

 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the

   register offset to write the PCS delay value.



Deprecated properties:

 - ctrl-module : phandle of the control module used by PHY driver to power on

drivers/phy/phy-ti-pipe3.c

+32 −2
Original line number Diff line number Diff line
@@ -65,6 +65,9 @@ 
#define PIPE3_PHY_TX_RX_POWERON		0x3

#define PIPE3_PHY_TX_RX_POWEROFF	0x0



#define PCIE_PCS_MASK			0xFF0000

#define PCIE_PCS_DELAY_COUNT_SHIFT	0x10



/*

 * This is an Empirical value that works, need to confirm the actual

 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 { 
	struct clk		*div_clk;

	struct pipe3_dpll_map	*dpll_map;

	struct regmap		*phy_power_syscon; /* ctrl. reg. acces */

	struct regmap		*pcs_syscon; /* ctrl. reg. acces */

	struct regmap		*dpll_reset_syscon; /* ctrl. reg. acces */

	unsigned int		dpll_reset_reg; /* reg. index within syscon */

	unsigned int		power_reg; /* power reg. index within syscon */

	unsigned int		pcie_pcs_reg; /* pcs reg. index in syscon */

	bool			sata_refclk_enabled;

};
@@ -269,10 +274,17 @@ static int ti_pipe3_init(struct phy *x) 
	 * 18-1804.

	 */

	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {

		if (!phy->pcs_syscon) {

			omap_control_pcie_pcs(phy->control_dev, 0x96);

			return 0;

		}



		val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;

		ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,

					 PCIE_PCS_MASK, val);

		return ret;

	}



	/* Bring it out of IDLE if it is IDLE */

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);

	if (val & PLL_IDLE) {
@@ -455,6 +467,24 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) 
		phy->control_dev = &control_pdev->dev;

	}



	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {

		phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,

								  "syscon-pcs");

		if (IS_ERR(phy->pcs_syscon)) {

			dev_dbg(dev,

				"can't get syscon-pcs, using omap control\n");

			phy->pcs_syscon = NULL;

		} else {

			if (of_property_read_u32_index(node,

						       "syscon-pcs", 1,

						       &phy->pcie_pcs_reg)) {

				dev_err(dev,

					"couldn't get pcie pcs reg. offset\n");

				return -EINVAL;

			}

		}

	}



	if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {

		phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,

							"syscon-pllreset");