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Commit 3ef62342 authored by Deepak S's avatar Deepak S Committed by Daniel Vetter
Browse files

drm/i915: Setup static bias for GPU 



Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.

v2: rename reg defn to match spec. (Ville)

v3: Updated bias setting for chv (Deepak)

Signed-off-by: default avatarDeepak S <deepak.s@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3126a660

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -670,6 +670,12 @@ enum skl_disp_power_wells { 
#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27

#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27

#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000

#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000





#define VLV_TURBO_SOC_OVERRIDE	0x04

#define 	VLV_OVERRIDE_EN	1

#define 	VLV_SOC_TDP_EN	(1 << 1)

#define 	VLV_BIAS_CPU_125_SOC_875 (6 << 2)

#define 	CHV_BIAS_CPU_50_SOC_50 (3 << 2)



#define VLV_CZ_CLOCK_TO_MILLI_SEC		100000

#define VLV_CZ_CLOCK_TO_MILLI_SEC		100000





/* vlv2 north clock has */

/* vlv2 north clock has */

drivers/gpu/drm/i915/intel_pm.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -5082,6 +5082,12 @@ static void cherryview_enable_rps(struct drm_device *dev) 
		   GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_DOWN_IDLE_AVG);

		   GEN6_RP_DOWN_IDLE_AVG);





	/* Setting Fixed Bias */

	val = VLV_OVERRIDE_EN |

		  VLV_SOC_TDP_EN |

		  CHV_BIAS_CPU_50_SOC_50;

	vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);



	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);





	/* RPS code assumes GPLL is used */

	/* RPS code assumes GPLL is used */
@@ -5166,6 +5172,12 @@ static void valleyview_enable_rps(struct drm_device *dev) 




	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);

	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);





	/* Setting Fixed Bias */

	val = VLV_OVERRIDE_EN |

		  VLV_SOC_TDP_EN |

		  VLV_BIAS_CPU_125_SOC_875;

	vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);



	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);





	/* RPS code assumes GPLL is used */

	/* RPS code assumes GPLL is used */