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Commit 3ea2d47e authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "dt-bindings: clock: Add gpu cc driver bindings for KONA"

parents dba422f4 d59dbedc

Documentation/devicetree/bindings/clock/qcom,camcc.txt

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Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding

-------------------------------------------------------------------



Required properties :

- compatible: must contain "qcom,camcc-sm8150", "qcom,camcc-sm8150-v2"

		   or "qcom,camcc-kona".

- reg: shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

- clock-names: Shall contain "cfg_ahb_clk"

- clocks: phandle + clock reference to the GCC AHB clock.

- vdd_<rail>-supply: The logic rail supply.

- #clock-cells: shall contain 1.



Example:

	clock_camcc: qcom,camcc@ad00000 {

		compatible = "qcom,camcc-kona";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		#clock-cells = <1>;

	};

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

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Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding

--------------------------------------------------------------------



Required properties :

- compatible: shall contain one of the following:

		"qcom,gpucc-kona".

- reg: shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

		Must contain "cc_base".

- #clock-cells: from common clock binding, shall contain 1.

- #reset-cells: from common reset binding, shall contain 1.

- vdd_cx-supply: The vdd_cx logic rail supply.

- vdd_mx-supply: The vdd_mx logic rail supply.



Optional properties :

- #power-domain-cells : from generic power domain binding, shall contain 1.



Example:



	clock_gpucc: clock-controller@3d90000 {

		compatible = "qcom,gpucc-kona";

		reg = <0x3d90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

arch/arm64/boot/dts/qcom/kona.dtsi

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@@ -764,9 +764,14 @@ 
		#reset-cells = <1>;

	};



	clock_camcc: qcom,camcc {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

	clock_camcc: qcom,camcc@ad00000 {

		compatible = "qcom,camcc-kona", "syscon";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_mm-supply = <&VDD_MMCX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

arch/arm64/configs/vendor/kona-perf_defconfig

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@@ -385,6 +385,7 @@ CONFIG_SPMI_PMIC_CLKDIV=y 
CONFIG_MSM_GCC_KONA=y

CONFIG_MSM_VIDEOCC_KONA=y

CONFIG_MSM_DISPCC_KONA=y

CONFIG_MSM_CAMCC_KONA=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_MAILBOX=y

arch/arm64/configs/vendor/kona_defconfig

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@@ -398,6 +398,7 @@ CONFIG_SPMI_PMIC_CLKDIV=y 
CONFIG_MSM_GCC_KONA=y

CONFIG_MSM_VIDEOCC_KONA=y

CONFIG_MSM_DISPCC_KONA=y

CONFIG_MSM_CAMCC_KONA=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_MAILBOX=y