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Commit 3d8b9e25 authored by Zhao Yan's avatar Zhao Yan Committed by Zhi Wang
Browse files

drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registers 



Each ring has a NOPID register and currently they are regarded as default
value of force_to_nonpriv registers in guest drivers

Signed-off-by: default avatarZhao Yan <yan.y.zhao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent b99f514f

drivers/gpu/drm/i915/gvt/cmd_parser.c

+8 −1
Original line number Diff line number Diff line
@@ -817,8 +817,15 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, 
{

	struct intel_gvt *gvt = s->vgpu->gvt;

	unsigned int data = cmd_val(s, index + 1);

	u32 ring_base;

	u32 nopid;

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	ring_base = dev_priv->engine[s->ring_id]->mmio_base;

	nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));



	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {

	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&

			data != nopid) {

		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",

			offset, data);

		return -EPERM;

drivers/gpu/drm/i915/gvt/handlers.c

+14 −8
Original line number Diff line number Diff line
@@ -474,21 +474,27 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, 
	unsigned int offset, void *p_data, unsigned int bytes)

{

	u32 reg_nonpriv = *(u32 *)p_data;

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	u32 ring_base;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	int ret = -EINVAL;



	if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",

			vgpu->id, offset, bytes);

	if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {

		gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",

			vgpu->id, ring_id, offset, bytes);

		return ret;

	}



	if (in_whitelist(reg_nonpriv)) {

	ring_base = dev_priv->engine[ring_id]->mmio_base;



	if (in_whitelist(reg_nonpriv) ||

		reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {

		ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,

			bytes);

	} else {

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",

			vgpu->id, reg_nonpriv);

	}

	} else

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",

			vgpu->id, reg_nonpriv, offset);



	return ret;

}