Merge tag 'drm-intel-fixes-2017-06-08' of... (3d76917f) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/i915/i915_drv.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -1235,6 +1235,15 @@ int i915_driver_load(struct pci_dev pdev, const struct pci_device_id ent)
		goto out_fini;

		pci_set_drvdata(pdev, &dev_priv->drm);
		/*
		* Disable the system suspend direct complete optimization, which can
		* leave the device suspended skipping the driver's suspend handlers
		* if the device was already runtime suspended. This is needed due to
		* the difference in our runtime and system suspend sequence and
		* becaue the HDA driver may require us to enable the audio power
		* domain during system suspend.
		*/
		pdev->dev_flags \|= PCI_DEV_FLAGS_NEEDS_RESUME;

		ret = i915_driver_init_early(dev_priv, ent);
		if (ret < 0)

drivers/gpu/drm/i915/i915_drv.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -2991,6 +2991,16 @@ static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
		return false;
		}

		static inline bool
		intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
		{
		#ifdef CONFIG_INTEL_IOMMU
		if (IS_BROXTON(dev_priv) && intel_iommu_gfx_mapped)
		return true;
		#endif
		return false;
		}

		int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
		int enable_ppgtt);

drivers/gpu/drm/i915/i915_gem.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -3298,6 +3298,10 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
		{
		int ret;

		/* If the device is asleep, we have no requests outstanding */
		if (!READ_ONCE(i915->gt.awake))
		return 0;

		if (flags & I915_WAIT_LOCKED) {
		struct i915_gem_timeline *tl;

drivers/gpu/drm/i915/i915_gem_gtt.c

+105 −1

Original line number	Diff line number	Diff line
		@@ -2191,6 +2191,101 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm,
		gen8_set_pte(&gtt_base[i], scratch_pte);
		}

		static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
		{
		struct drm_i915_private *dev_priv = vm->i915;

		/*
		* Make sure the internal GAM fifo has been cleared of all GTT
		* writes before exiting stop_machine(). This guarantees that
		* any aperture accesses waiting to start in another process
		* cannot back up behind the GTT writes causing a hang.
		* The register can be any arbitrary GAM register.
		*/
		POSTING_READ(GFX_FLSH_CNTL_GEN6);
		}

		struct insert_page {
		struct i915_address_space *vm;
		dma_addr_t addr;
		u64 offset;
		enum i915_cache_level level;
		};

		static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
		{
		struct insert_page *arg = _arg;

		gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
		bxt_vtd_ggtt_wa(arg->vm);

		return 0;
		}

		static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
		dma_addr_t addr,
		u64 offset,
		enum i915_cache_level level,
		u32 unused)
		{
		struct insert_page arg = { vm, addr, offset, level };

		stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
		}

		struct insert_entries {
		struct i915_address_space *vm;
		struct sg_table *st;
		u64 start;
		enum i915_cache_level level;
		};

		static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
		{
		struct insert_entries *arg = _arg;

		gen8_ggtt_insert_entries(arg->vm, arg->st, arg->start, arg->level, 0);
		bxt_vtd_ggtt_wa(arg->vm);

		return 0;
		}

		static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
		struct sg_table *st,
		u64 start,
		enum i915_cache_level level,
		u32 unused)
		{
		struct insert_entries arg = { vm, st, start, level };

		stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
		}

		struct clear_range {
		struct i915_address_space *vm;
		u64 start;
		u64 length;
		};

		static int bxt_vtd_ggtt_clear_range__cb(void *_arg)
		{
		struct clear_range *arg = _arg;

		gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
		bxt_vtd_ggtt_wa(arg->vm);

		return 0;
		}

		static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm,
		u64 start,
		u64 length)
		{
		struct clear_range arg = { vm, start, length };

		stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL);
		}

		static void gen6_ggtt_clear_range(struct i915_address_space *vm,
		u64 start, u64 length)
		{
		@@ -2785,6 +2880,14 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)

		ggtt->base.insert_entries = gen8_ggtt_insert_entries;

		/* Serialize GTT updates with aperture access on BXT if VT-d is on. */
		if (intel_ggtt_update_needs_vtd_wa(dev_priv)) {
		ggtt->base.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
		ggtt->base.insert_page = bxt_vtd_ggtt_insert_page__BKL;
		if (ggtt->base.clear_range != nop_clear_range)
		ggtt->base.clear_range = bxt_vtd_ggtt_clear_range__BKL;
		}

		ggtt->invalidate = gen6_ggtt_invalidate;

		return ggtt_probe_common(ggtt, size);
		@@ -2997,6 +3100,7 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915)

		void i915_ggtt_disable_guc(struct drm_i915_private *i915)
		{
		if (i915->ggtt.invalidate == guc_ggtt_invalidate)
		i915->ggtt.invalidate = gen6_ggtt_invalidate;
		}

drivers/gpu/drm/i915/i915_gem_tiling.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -278,7 +278,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
		obj->mm.quirked = false;
		}
		if (!i915_gem_object_is_tiled(obj)) {
		GEM_BUG_ON(!obj->mm.quirked);
		GEM_BUG_ON(obj->mm.quirked);
		__i915_gem_object_pin_pages(obj);
		obj->mm.quirked = true;
		}