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Commit 3d0f4e5f authored by Thierry Reding's avatar Thierry Reding
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clk: tegra: Use correct parent for dpaux clock 



The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 1ec7032a
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