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Commit 3c626203 authored by Can Guo's avatar Can Guo
Browse files

ARM: dts: qcom: add removable UFS device support on Kona platforms 

This change adds the removable UFS device related nodes and properties to
Kona device trees to support UFS cards on Kona platforms.

Change-Id: I04d92c1fa0066d2f50b8492cf516ad6cc4857d17
parent c6c37440

qcom/kona-cdp.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -81,6 +81,32 @@ 
	status = "ok";

};



&ufsphy_card {

	compatible = "qcom,ufs-phy-qmp-v4-card";



	vdda-phy-supply = <&pm8150_l5>; /* 0.88v */

	vdda-pll-supply = <&pm8150_l9>; /* 1.2v */

	vdda-phy-max-microamp = <87100>;

	vdda-pll-max-microamp = <18300>;



	status = "ok";

};



&ufshc_card {

	vdd-hba-supply = <&ufs_card_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8150a_l9>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&pm8150_s4>;

	vcc-max-microamp = <500000>;

	vccq2-max-microamp = <400000>;



	qcom,vddp-ref-clk-supply = <&pm8150_l6>;

	qcom,vddp-ref-clk-max-microamp = <100>;



	status = "ok";

};



&soc {

	gpio_keys {

		compatible = "gpio-keys";

qcom/kona-mtp.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -81,6 +81,32 @@ 
	status = "ok";

};



&ufsphy_card {

	compatible = "qcom,ufs-phy-qmp-v4-card";



	vdda-phy-supply = <&pm8150_l5>; /* 0.88v */

	vdda-pll-supply = <&pm8150_l9>; /* 1.2v */

	vdda-phy-max-microamp = <87100>;

	vdda-pll-max-microamp = <18300>;



	status = "ok";

};



&ufshc_card {

	vdd-hba-supply = <&ufs_card_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8150a_l9>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&pm8150_s4>;

	vcc-max-microamp = <500000>;

	vccq2-max-microamp = <400000>;



	qcom,vddp-ref-clk-supply = <&pm8150_l6>;

	qcom,vddp-ref-clk-max-microamp = <100>;



	status = "ok";

};



&soc {

	gpio_keys {

		compatible = "gpio-keys";

qcom/kona-rumi.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -42,6 +42,32 @@ 
	status = "ok";

};



&ufsphy_card {

	compatible = "qcom,ufs-phy-qrbtc-sdm845";



	vdda-phy-supply = <&pm8150_l5>; /* 0.88v */

	vdda-pll-supply = <&pm8150_l9>; /* 1.2v */

	vdda-phy-max-microamp = <87100>;

	vdda-pll-max-microamp = <18300>;



	status = "ok";

};



&ufshc_card {

	vdd-hba-supply = <&ufs_card_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&pm8150a_l9>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&pm8150_s4>;

	vcc-max-microamp = <500000>;

	vccq2-max-microamp = <400000>;



	qcom,vddp-ref-clk-supply = <&pm8150_l6>;

	qcom,vddp-ref-clk-max-microamp = <100>;



	status = "ok";

};



&soc {

	#address-cells = <1>;

	#size-cells = <1>;

qcom/kona.dtsi

+91 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 


	aliases {

		ufshc1 = &ufshc_mem; /* Embedded UFS slot */

		ufshc2 = &ufshc_card; /* Removable UFS slot */

		sdhc2 = &sdhc_2; /* SDC2 SD card slot */

		pci-domain0 = &pcie0; /* PCIe0 domain */

		pci-domain1 = &pcie1; /* PCIe1 domain */
@@ -2111,6 +2112,96 @@ 
		status = "disabled";

	};



	ufsphy_card: ufsphy_card@1da7000 {

		reg = <0x1da7000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		lanes-per-direction = <1>;



		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_1X_CLKREF_EN>,

			<&clock_gcc GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK>;



		status = "disabled";

	};



	ufshc_card: ufshc_card@1da4000 {

		compatible = "qcom,ufshc";

		reg = <0x1da4000 0x3000>;

		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&ufsphy_card>;

		phy-names = "ufsphy";



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_CARD_AXI_HW_CTL_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_CARD_AHB_CLK>,

			<&clock_gcc GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>;

		freq-table-hz =

			<50000000 200000000>,

			<0 0>,

			<0 0>,

			<37500000 150000000>,

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_card";

		qcom,msm-bus,num-cases = <9>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		<122 512 0 0>, <1 756 0 0>,          /* No vote */

		<122 512 922 0>, <1 756 1000 0>,     /* PWM G1 */

		<122 512 127796 0>, <1 756 1000 0>,  /* HS G1 RA */

		<122 512 255591 0>, <1 756 1000 0>,  /* HS G2 RA */

		<122 512 2097152 0>, <1 756 102400 0>,  /* HS G3 RA */

		<122 512 149422 0>, <1 756 1000 0>,  /* HS G1 RB */

		<122 512 298189 0>, <1 756 1000 0>,  /* HS G2 RB */

		<122 512 2097152 0>, <1 756 102400 0>,  /* HS G3 RB */

		<122 512 7643136 0>, <1 756 307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cpu-group-latency-us = <70 70>;

		qcom,pm-qos-default-cpu = <0>;



		/*

		 * Note: this instance doesn't have control over UFS device

		 * reset

		 */



		resets = <&clock_gcc GCC_UFS_CARD_BCR>;

		reset-names = "core_reset";



		status = "disabled";

	};



	ipcc_mproc: qcom,ipcc@408000 {

		compatible = "qcom,ipcc";

		reg = <0x408000 0x1000>;