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Commit 3c5b1d92 authored by Tirumalesh Chalamarla's avatar Tirumalesh Chalamarla Committed by Marc Zyngier
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arm64: KVM: Configure TCR_EL2.PS at runtime



Setting TCR_EL2.PS to 40 bits is wrong on systems with less that
less than 40 bits of physical addresses. and breaks KVM on systems
where the RAM is above 40 bits.

This patch uses ID_AA64MMFR0_EL1.PARange to set TCR_EL2.PS dynamically,
just like we already do for VTCR_EL2.PS.

[Marc: rewrote commit message, patch tidy up]

Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarTirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent b3aff6cc
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+0 −2
Original line number Diff line number Diff line
@@ -107,8 +107,6 @@
#define TCR_EL2_MASK	(TCR_EL2_TG0 | TCR_EL2_SH0 | \
			 TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)

#define TCR_EL2_FLAGS	(TCR_EL2_RES1 | TCR_EL2_PS_40B)

/* VTCR_EL2 Registers bits */
#define VTCR_EL2_RES1		(1 << 31)
#define VTCR_EL2_PS_MASK	(7 << 16)
+7 −5
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ __do_hyp_init:
	mrs	x4, tcr_el1
	ldr	x5, =TCR_EL2_MASK
	and	x4, x4, x5
	ldr	x5, =TCR_EL2_FLAGS
	mov	x5, #TCR_EL2_RES1
	orr	x4, x4, x5

#ifndef CONFIG_ARM64_VA_BITS_48
@@ -85,15 +85,17 @@ __do_hyp_init:
	ldr_l	x5, idmap_t0sz
	bfi	x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
#endif
	msr	tcr_el2, x4

	ldr	x4, =VTCR_EL2_FLAGS
	/*
	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in
	 * VTCR_EL2.
	 * TCR_EL2 and VTCR_EL2.
	 */
	mrs	x5, ID_AA64MMFR0_EL1
	bfi	x4, x5, #16, #3

	msr	tcr_el2, x4

	ldr	x4, =VTCR_EL2_FLAGS
	bfi	x4, x5, #16, #3
	/*
	 * Read the VMIDBits bits from ID_AA64MMFR1_EL1 and set the VS bit in
	 * VTCR_EL2.