Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3c44780b authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
Browse files

perf, x86: Disable PEBS on clovertown chips 



This CPU has just too many handycaps to be really useful.

Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100305154128.890278662@chello.nl>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 3adaebd6

arch/x86/kernel/cpu/perf_event.c

+4 −0
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ struct x86_pmu { 
	void		(*put_event_constraints)(struct cpu_hw_events *cpuc,

						 struct perf_event *event);

	struct event_constraint *event_constraints;

	void		(*quirks)(void);



	void		(*cpu_prepare)(int cpu);

	void		(*cpu_starting)(int cpu);
@@ -1373,6 +1374,9 @@ void __init init_hw_perf_events(void) 


	pr_cont("%s PMU driver.\n", x86_pmu.name);



	if (x86_pmu.quirks)

		x86_pmu.quirks();



	if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {

		WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",

		     x86_pmu.num_events, X86_PMC_MAX_GENERIC);

arch/x86/kernel/cpu/perf_event_intel.c

+27 −0
Original line number Diff line number Diff line
@@ -792,6 +792,32 @@ static __initconst struct x86_pmu intel_pmu = { 
	.cpu_dying		= fini_debug_store_on_cpu,

};



static void intel_clovertown_quirks(void)

{

	/*

	 * PEBS is unreliable due to:

	 *

	 *   AJ67  - PEBS may experience CPL leaks

	 *   AJ68  - PEBS PMI may be delayed by one event

	 *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]

	 *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS

	 *

	 * AJ67 could be worked around by restricting the OS/USR flags.

	 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.

	 *

	 * AJ106 could possibly be worked around by not allowing LBR

	 *       usage from PEBS, including the fixup.

	 * AJ68  could possibly be worked around by always programming

	 * 	 a pebs_event_reset[0] value and coping with the lost events.

	 *

	 * But taken together it might just make sense to not enable PEBS on

	 * these chips.

	 */

	printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");

	x86_pmu.pebs = 0;

	x86_pmu.pebs_constraints = NULL;

}



static __init int intel_pmu_init(void)

{

	union cpuid10_edx edx;
@@ -856,6 +882,7 @@ static __init int intel_pmu_init(void) 
		break;



	case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */

		x86_pmu.quirks = intel_clovertown_quirks;

	case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */

	case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */

	case 29: /* six-core 45 nm xeon "Dunnington" */