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Commit 3c0d551e authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:

 - move pci_uevent_ers() out of pci.h (Michael Ellerman)

 - skip ASPM common clock warning if BIOS already configured it (Sinan
   Kaya)

 - fix ASPM Coverity warning about threshold_ns (Gustavo A. R. Silva)

 - remove last user of pci_get_bus_and_slot() and the function itself
   (Sinan Kaya)

 - add decoding for 16 GT/s link speed (Jay Fang)

 - add interfaces to get max link speed and width (Tal Gilboa)

 - add pcie_bandwidth_capable() to compute max supported link bandwidth
   (Tal Gilboa)

 - add pcie_bandwidth_available() to compute bandwidth available to
   device (Tal Gilboa)

 - add pcie_print_link_status() to log link speed and whether it's
   limited (Tal Gilboa)

 - use PCI core interfaces to report when device performance may be
   limited by its slot instead of doing it in each driver (Tal Gilboa)

 - fix possible cpqphp NULL pointer dereference (Shawn Lin)

 - rescan more of the hierarchy on ACPI hotplug to fix Thunderbolt/xHCI
   hotplug (Mika Westerberg)

 - add support for PCI I/O port space that's neither directly accessible
   via CPU in/out instructions nor directly mapped into CPU physical
   memory space. This is fairly intrusive and includes minor changes to
   interfaces used for I/O space on most platforms (Zhichang Yuan, John
   Garry)

 - add support for HiSilicon Hip06/Hip07 LPC I/O space (Zhichang Yuan,
   John Garry)

 - use PCI_EXP_DEVCTL2_COMP_TIMEOUT in rapidio/tsi721 (Bjorn Helgaas)

 - remove possible NULL pointer dereference in of_pci_bus_find_domain_nr()
   (Shawn Lin)

 - report quirk timings with dev_info (Bjorn Helgaas)

 - report quirks that take longer than 10ms (Bjorn Helgaas)

 - add and use Altera Vendor ID (Johannes Thumshirn)

 - tidy Makefiles and comments (Bjorn Helgaas)

 - don't set up INTx if MSI or MSI-X is enabled to align cris, frv,
   ia64, and mn10300 with x86 (Bjorn Helgaas)

 - move pcieport_if.h to drivers/pci/pcie/ to encapsulate it (Frederick
   Lawler)

 - merge pcieport_if.h into portdrv.h (Bjorn Helgaas)

 - move workaround for BIOS PME issue from portdrv to PCI core (Bjorn
   Helgaas)

 - completely disable portdrv with "pcie_ports=compat" (Bjorn Helgaas)

 - remove portdrv link order dependency (Bjorn Helgaas)

 - remove support for unused VC portdrv service (Bjorn Helgaas)

 - simplify portdrv feature permission checking (Bjorn Helgaas)

 - remove "pcie_hp=nomsi" parameter (use "pci=nomsi" instead) (Bjorn
   Helgaas)

 - remove unnecessary "pcie_ports=auto" parameter (Bjorn Helgaas)

 - use cached AER capability offset (Frederick Lawler)

 - don't enable DPC if BIOS hasn't granted AER control (Mika Westerberg)

 - rename pcie-dpc.c to dpc.c (Bjorn Helgaas)

 - use generic pci_mmap_resource_range() instead of powerpc and xtensa
   arch-specific versions (David Woodhouse)

 - support arbitrary PCI host bridge offsets on sparc (Yinghai Lu)

 - remove System and Video ROM reservations on sparc (Bjorn Helgaas)

 - probe for device reset support during enumeration instead of runtime
   (Bjorn Helgaas)

 - add ACS quirk for Ampere (née APM) root ports (Feng Kan)

 - add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas
   Vincent-Cross)

 - protect device restore with device lock (Sinan Kaya)

 - handle failure of FLR gracefully (Sinan Kaya)

 - handle CRS (config retry status) after device resets (Sinan Kaya)

 - skip various config reads for SR-IOV VFs as an optimization
   (KarimAllah Ahmed)

 - consolidate VPD code in vpd.c (Bjorn Helgaas)

 - add Tegra dependency on PCI_MSI_IRQ_DOMAIN (Arnd Bergmann)

 - add DT support for R-Car r8a7743 (Biju Das)

 - fix a PCI_EJECT vs PCI_BUS_RELATIONS race condition in Hyper-V host
   bridge driver that causes a general protection fault (Dexuan Cui)

 - fix Hyper-V host bridge hang in MSI setup on 1-vCPU VMs with SR-IOV
   (Dexuan Cui)

 - fix Hyper-V host bridge hang when ejecting a VF before setting up MSI
   (Dexuan Cui)

 - make several structures static (Fengguang Wu)

 - increase number of MSI IRQs supported by Synopsys DesignWare bridges
   from 32 to 256 (Gustavo Pimentel)

 - implemented multiplexed IRQ domain API and remove obsolete MSI IRQ
   API from DesignWare drivers (Gustavo Pimentel)

 - add Tegra power management support (Manikanta Maddireddy)

 - add Tegra loadable module support (Manikanta Maddireddy)

 - handle 64-bit BARs correctly in endpoint support (Niklas Cassel)

 - support optional regulator for HiSilicon STB (Shawn Guo)

 - use regulator bulk API for Qualcomm apq8064 (Srinivas Kandagatla)

 - support power supplies for Qualcomm msm8996 (Srinivas Kandagatla)

* tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (123 commits)
  MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver
  HISI LPC: Add ACPI support
  ACPI / scan: Do not enumerate Indirect IO host children
  ACPI / scan: Rename acpi_is_serial_bus_slave() for more general use
  HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings
  of: Add missing I/O range exception for indirect-IO devices
  PCI: Apply the new generic I/O management on PCI IO hosts
  PCI: Add fwnode handler as input param of pci_register_io_range()
  PCI: Remove __weak tag from pci_register_io_range()
  MAINTAINERS: Add missing /drivers/pci/cadence directory entry
  fm10k: Report PCIe link properties with pcie_print_link_status()
  net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
  net/mlx5: Report PCIe link properties with pcie_print_link_status()
  net/mlx4_core: Report PCIe link properties with pcie_print_link_status()
  PCI: Add pcie_print_link_status() to log link speed and whether it's limited
  PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
  misc: pci_endpoint_test: Handle 64-bit BARs properly
  PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly
  PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing
  PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar
  ...
parents 19fd08b8 5f764419

Documentation/admin-guide/kernel-parameters.txt

+7 −12
Original line number Diff line number Diff line
@@ -3154,18 +3154,13 @@ 
		force	Enable ASPM even on devices that claim not to support it.

			WARNING: Forcing ASPM on may cause system lockups.



	pcie_hp=	[PCIE] PCI Express Hotplug driver options:

		nomsi	Do not use MSI for PCI Express Native Hotplug (this

			makes all PCIe ports use INTx for hotplug services).



	pcie_ports=	[PCIE] PCIe ports handling:

		auto	Ask the BIOS whether or not to use native PCIe services

			associated with PCIe ports (PME, hot-plug, AER).  Use

			them only if that is allowed by the BIOS.

		native	Use native PCIe services associated with PCIe ports

			unconditionally.

		compat	Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe

			ports driver.

	pcie_ports=	[PCIE] PCIe port services handling:

		native	Use native PCIe services (PME, AER, DPC, PCIe hotplug)

			even if the platform doesn't give the OS permission to

			use them.  This may cause conflicts if the platform

			also tries to use these services.

		compat	Disable native PCIe services (PME, AER, DPC, PCIe

			hotplug).



	pcie_port_pm=	[PCIE] PCIe port power management handling:

		off	Disable power management of all PCIe ports

Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt

0 → 100644
+33 −0
Original line number Diff line number Diff line 
Hisilicon Hip06 Low Pin Count device

  Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which

  provides I/O access to some legacy ISA devices.

  Hip06 is based on arm64 architecture where there is no I/O space. So, the

  I/O ports here are not CPU addresses, and there is no 'ranges' property in

  LPC device node.



Required properties:

- compatible:  value should be as follows:

	(a) "hisilicon,hip06-lpc"

	(b) "hisilicon,hip07-lpc"

- #address-cells: must be 2 which stick to the ISA/EISA binding doc.

- #size-cells: must be 1 which stick to the ISA/EISA binding doc.

- reg: base memory range where the LPC register set is mapped.



Note:

  The node name before '@' must be "isa" to represent the binding stick to the

  ISA/EISA binding specification.



Example:



isa@a01b0000 {

	compatible = "hisilicon,hip06-lpc";

	#address-cells = <2>;

	#size-cells = <1>;

	reg = <0x0 0xa01b0000 0x0 0x1000>;



	ipmi0: bt@e4 {

		compatible = "ipmi-bt";

		device_type = "ipmi";

		reg = <0x01 0xe4 0x04>;

	};

};

Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ Required properties 


Optional properties:

- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.

- vpcie-supply: The regulator in charge of PCIe port power.

- phys: List of phandle and phy mode specifier, should be 0.

- phy-names: Must be "phy".

Documentation/devicetree/bindings/pci/mediatek-pcie.txt

+3 −8
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ Examples for MT7623: 
		#reset-cells = <1>;

	};



	pcie: pcie-controller@1a140000 {

	pcie: pcie@1a140000 {

		compatible = "mediatek,mt7623-pcie";

		device_type = "pci";

		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
@@ -111,7 +111,6 @@ Examples for MT7623: 
			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */



		pcie@0,0 {

			device_type = "pci";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;
@@ -123,7 +122,6 @@ Examples for MT7623: 
		};



		pcie@1,0 {

			device_type = "pci";

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;
@@ -135,7 +133,6 @@ Examples for MT7623: 
		};



		pcie@2,0 {

			device_type = "pci";

			reg = <0x1000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;
@@ -148,6 +145,7 @@ Examples for MT7623: 
	};



Examples for MT2712:



	pcie: pcie@11700000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";
@@ -169,7 +167,6 @@ Examples for MT2712: 
		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;



		pcie0: pcie@0,0 {

			device_type = "pci";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;
@@ -189,7 +186,6 @@ Examples for MT2712: 
		};



		pcie1: pcie@1,0 {

			device_type = "pci";

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;
@@ -210,6 +206,7 @@ Examples for MT2712: 
	};



Examples for MT7622:



	pcie: pcie@1a140000 {

		compatible = "mediatek,mt7622-pcie";

		device_type = "pci";
@@ -243,7 +240,6 @@ Examples for MT7622: 
		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;



		pcie0: pcie@0,0 {

			device_type = "pci";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;
@@ -263,7 +259,6 @@ Examples for MT7622: 
		};



		pcie1: pcie@1,0 {

			device_type = "pci";

			reg = <0x0800 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

Documentation/devicetree/bindings/pci/qcom,pcie.txt

+4 −0
Original line number Diff line number Diff line
@@ -189,6 +189,10 @@ 
	Value type: <phandle>

	Definition: A phandle to the analog power supply for IC which generates

		    reference clock

- vddpe-3v3-supply:

	Usage: optional

	Value type: <phandle>

	Definition: A phandle to the PCIe endpoint power supply



- phys:

	Usage: required for apq8084