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Commit 3c009e3c authored by Jackie Li's avatar Jackie Li Committed by Joonas Lahtinen
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drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset 



GuC related exported functions should start with "intel_guc_" prefix and
pass intel_guc as the first parameter since its GuC related. Current
guc_ggtt_offset() failed to follow this code convention and this is a
problem for future patches that needs to access intel_guc data to verify
the GGTT offset against the GuC WOPCM top.

This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
the related code to pass intel_guc pointer to this function call, so that
we can have a unified coding style for GuC code and also enable the future
patches to get GuC related data from intel_guc to do the offset
verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
intel_guc_regs.h to intel_guc.h since it is not GuC register related
definition.

v8:
 - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
 - Updated commit message to explain to reason and motivation to add
   intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)

v9:
 - Fixed code alignment issue due to line break (Chris)

v10:
 - Removed unnecessary comments, redundant code and avoided reuse variable
   to avoid potential issues (Joonas)

v13:
 - Updated the ordering of s-o-b/cc/r-b tags (Sagar)

Signed-off-by: default avatarJackie Li <yaodong.li@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v8)
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v11)
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v12)
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1520987574-19351-1-git-send-email-yaodong.li@intel.com
parent 62801bf6

drivers/gpu/drm/i915/intel_guc.c

+6 −5
Original line number Diff line number Diff line
@@ -269,8 +269,9 @@ void intel_guc_init_params(struct intel_guc *guc) 


	/* If GuC submission is enabled, set up additional parameters here */

	if (USES_GUC_SUBMISSION(dev_priv)) {

		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;

		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);

		u32 ads = intel_guc_ggtt_offset(guc,

						guc->ads_vma) >> PAGE_SHIFT;

		u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);

		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;



		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
@@ -447,7 +448,7 @@ int intel_guc_suspend(struct intel_guc *guc) 
	u32 data[] = {

		INTEL_GUC_ACTION_ENTER_S_STATE,

		GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */

		guc_ggtt_offset(guc->shared_data)

		intel_guc_ggtt_offset(guc, guc->shared_data)

	};



	return intel_guc_send(guc, data, ARRAY_SIZE(data));
@@ -471,7 +472,7 @@ int intel_guc_reset_engine(struct intel_guc *guc, 
	data[3] = 0;

	data[4] = 0;

	data[5] = guc->execbuf_client->stage_id;

	data[6] = guc_ggtt_offset(guc->shared_data);

	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);



	return intel_guc_send(guc, data, ARRAY_SIZE(data));

}
@@ -485,7 +486,7 @@ int intel_guc_resume(struct intel_guc *guc) 
	u32 data[] = {

		INTEL_GUC_ACTION_EXIT_S_STATE,

		GUC_POWER_D0,

		guc_ggtt_offset(guc->shared_data)

		intel_guc_ggtt_offset(guc, guc->shared_data)

	};



	return intel_guc_send(guc, data, ARRAY_SIZE(data));

drivers/gpu/drm/i915/intel_guc.h

+12 −2
Original line number Diff line number Diff line
@@ -100,13 +100,23 @@ static inline void intel_guc_notify(struct intel_guc *guc) 
	guc->notify(guc);

}



/*

/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */

#define GUC_GGTT_TOP	0xFEE00000



/**

 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma

 * @guc: intel_guc structure.

 * @vma: i915 graphics virtual memory area.

 *

 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),

 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is

 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects

 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.

 *

 * Return: GGTT offset that meets the GuC gfx address requirement.

 */

static inline u32 guc_ggtt_offset(struct i915_vma *vma)

static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,

					struct i915_vma *vma)

{

	u32 offset = i915_ggtt_offset(vma);

drivers/gpu/drm/i915/intel_guc_ads.c

+4 −4
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static void guc_policies_init(struct guc_policies *policies) 
int intel_guc_ads_create(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_i915(guc);

	struct i915_vma *vma;

	struct i915_vma *vma, *kernel_ctx_vma;

	struct page *page;

	/* The ads obj includes the struct itself and buffers passed to GuC */

	struct {
@@ -121,9 +121,9 @@ int intel_guc_ads_create(struct intel_guc *guc) 
	 * to find it. Note that we have to skip our header (1 page),

	 * because our GuC shared data is there.

	 */

	kernel_ctx_vma = dev_priv->kernel_context->engine[RCS].state;

	blob->ads.golden_context_lrca =

		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +

		skipped_offset;

		intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;



	/*

	 * The GuC expects us to exclude the portion of the context image that
@@ -135,7 +135,7 @@ int intel_guc_ads_create(struct intel_guc *guc) 
		blob->ads.eng_state_size[engine->guc_id] =

			engine->context_size - skipped_size;



	base = guc_ggtt_offset(vma);

	base = intel_guc_ggtt_offset(guc, vma);

	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);

	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);

	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);

drivers/gpu/drm/i915/intel_guc_ct.c

+3 −2
Original line number Diff line number Diff line
@@ -156,7 +156,8 @@ static int ctch_init(struct intel_guc *guc, 
		err = PTR_ERR(blob);

		goto err_vma;

	}

	DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));

	DRM_DEBUG_DRIVER("CT: vma base=%#x\n",

			 intel_guc_ggtt_offset(guc, ctch->vma));



	/* store pointers to desc and cmds */

	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
@@ -202,7 +203,7 @@ static int ctch_open(struct intel_guc *guc, 
	}



	/* vma should be already allocated and map'ed */

	base = guc_ggtt_offset(ctch->vma);

	base = intel_guc_ggtt_offset(guc, ctch->vma);



	/* (re)initialize descriptors

	 * cmds buffers are in the second half of the blob page

drivers/gpu/drm/i915/intel_guc_fw.c

+1 −1
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma) 
	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);



	/* Set the source address for the new blob */

	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;

	offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;

	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));

	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);