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Commit 3bba73b1 authored by Thomas Gleixner's avatar Thomas Gleixner
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x86/cpufeature: Move RING3MWAIT feature to avoid conflicts 



The original feature bit is used in a different branch already. Move it to
scattered bits.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 4d8bb006

arch/x86/include/asm/cpufeatures.h

+2 −2
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ 
#define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */

#define X86_FEATURE_RING3MWAIT	( 3*32+25) /* ring 3 MONITOR/MWAIT */

/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */

#define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */

#define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */

#define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
@@ -186,7 +186,7 @@ 
 *

 * Reuse free bits when adding new feature flags!

 */



#define X86_FEATURE_RING3MWAIT	( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_CAT_L3	( 7*32+ 4) /* Cache Allocation Technology L3 */