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Commit 3b358cda authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Kill the remaining CHV HBR2 leftovers 



AFAIK CHV was supposed to have HBR2 originally, but in the end the feature
was dropped. We still have some code leftovers from those early days.
Eliminate them.

The extra bit for the training pattern seems to be dead in the hardware.
I can set it (in fact I can set almost any reserved bit in the
registers) but it doesn't seem to interfere with the operation of the
hardware. Either that or I'm very lucky that my displays complete link
training with the incorrect pattern being sent out.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180302095656.19662-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
parent e4006713

drivers/gpu/drm/i915/i915_reg.h

+0 −2
Original line number Diff line number Diff line
@@ -4943,8 +4943,6 @@ enum { 
#define   DP_LINK_TRAIN_OFF		(3 << 28)

#define   DP_LINK_TRAIN_MASK		(3 << 28)

#define   DP_LINK_TRAIN_SHIFT		28

#define   DP_LINK_TRAIN_PAT_3_CHV	(1 << 14)

#define   DP_LINK_TRAIN_MASK_CHV	((3 << 28)|(1<<14))



/* CPT Link training mode */

#define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)

drivers/gpu/drm/i915/intel_dp.c

+4 −16
Original line number Diff line number Diff line
@@ -91,8 +91,6 @@ static const struct dp_link_dpll chv_dpll[] = { 
		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },

	{ 270000,	/* m2_int = 27, m2_fraction = 0 */

		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },

	{ 540000,	/* m2_int = 27, m2_fraction = 0 */

		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }

};



/**
@@ -2900,9 +2898,6 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, 
		}



	} else {

		if (IS_CHERRYVIEW(dev_priv))

			*DP &= ~DP_LINK_TRAIN_MASK_CHV;

		else

		*DP &= ~DP_LINK_TRAIN_MASK;



		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
@@ -2916,12 +2911,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, 
			*DP |= DP_LINK_TRAIN_PAT_2;

			break;

		case DP_TRAINING_PATTERN_3:

			if (IS_CHERRYVIEW(dev_priv)) {

				*DP |= DP_LINK_TRAIN_PAT_3_CHV;

			} else {

			DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");

			*DP |= DP_LINK_TRAIN_PAT_2;

			}

			break;

		}

	}
@@ -3660,9 +3651,6 @@ intel_dp_link_down(struct intel_encoder *encoder, 
		DP &= ~DP_LINK_TRAIN_MASK_CPT;

		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

	} else {

		if (IS_CHERRYVIEW(dev_priv))

			DP &= ~DP_LINK_TRAIN_MASK_CHV;

		else

		DP &= ~DP_LINK_TRAIN_MASK;

		DP |= DP_LINK_TRAIN_PAT_IDLE;

	}