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Commit 3b120ab7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm 

* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
  ARM: 7182/1: ARM cpu topology: fix warning
  ARM: 7181/1: Restrict kprobes probing SWP instructions to ARMv5 and below
  ARM: 7180/1: Change kprobes testcase with unpredictable STRD instruction
  ARM: 7177/1: GIC: avoid skipping non-existent PPIs in irq_start calculation
  ARM: 7176/1: cpu_pm: register GIC PM notifier only once
  ARM: 7175/1: add subname parameter to mfp_set_groupg callers
  ARM: 7174/1: Fix build error in kprobes test code on Thumb2 kernels
  ARM: 7172/1: dma: Drop GFP_COMP for DMA memory allocations
  ARM: 7171/1: unwind: add unwind directives to bitops assembly macros
  ARM: 7170/2: fix compilation breakage in entry-armv.S
  ARM: 7168/1: use cache type functions for arch_get_unmapped_area
  ARM: perf: check that we have a platform device when reserving PMU
  ARM: 7166/1: Use PMD_SHIFT instead of PGDIR_SHIFT in dma-consistent.c
  ARM: 7165/2: PL330: Fix typo in _prepare_ccr()
  ARM: 7163/2: PL330: Only register usable channels
  ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds
  ARM: 7161/1: errata: no automatic store buffer drain
  ARM: perf: initialise used_mask for fake PMU during validation
  ARM: PMU: remove pmu_init declaration
  ARM: PMU: re-export release_pmu symbol to modules
parents b930c264 4cbd6b16

arch/arm/Kconfig

+16 −4
Original line number Diff line number Diff line
@@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231 
	  capabilities of the processor.



config PL310_ERRATA_588369

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0

	help

	   The PL310 L2 cache controller implements three types of Clean &
@@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789 
	  entries regardless of the ASID.



config PL310_ERRATA_727915

	bool "Background Clean & Invalidate by Way operation can cause data corruption"

	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"

	depends on CACHE_L2X0

	help

	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
@@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472 
	  operation is received by a CPU before the ICIALLUIS has completed,

	  potentially leading to corrupted entries in the cache or TLB.



config ARM_ERRATA_753970

	bool "ARM errata: cache sync operation may be faulty"

config PL310_ERRATA_753970

	bool "PL310 errata: cache sync operation may be faulty"

	depends on CACHE_PL310

	help

	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.
@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369 
	  relevant cache maintenance functions and sets a specific bit

	  in the diagnostic control register of the SCU.



config PL310_ERRATA_769419

	bool "PL310 errata: no automatic Store Buffer drain"

	depends on CACHE_L2X0

	help

	  On revisions of the PL310 prior to r3p2, the Store Buffer does

	  not automatically drain. This can cause normal, non-cacheable

	  writes to be retained when the memory system is idle, leading

	  to suboptimal I/O performance for drivers using coherent DMA.

	  This option adds a write barrier to the cpu_idle loop so that,

	  on systems with an outer cache, the store buffer is drained

	  explicitly.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/common/gic.c

+10 −6
Original line number Diff line number Diff line
@@ -526,6 +526,7 @@ static void __init gic_pm_init(struct gic_chip_data *gic) 
		sizeof(u32));

	BUG_ON(!gic->saved_ppi_conf);



	if (gic == &gic_data[0])

		cpu_pm_register_notifier(&gic_notifier_block);

}

#else
@@ -581,13 +582,16 @@ void __init gic_init(unsigned int gic_nr, int irq_start, 
	 * For primary GICs, skip over SGIs.

	 * For secondary GICs, skip over PPIs, too.

	 */

	domain->hwirq_base = 32;

	if (gic_nr == 0) {

		gic_cpu_base_addr = cpu_base;



		if ((irq_start & 31) > 0) {

			domain->hwirq_base = 16;

		if (irq_start > 0)

			if (irq_start != -1)

				irq_start = (irq_start & ~31) + 16;

	} else

		domain->hwirq_base = 32;

		}

	}



	/*

	 * Find out how many interrupts are supported.

arch/arm/common/pl330.c

+9 −3
Original line number Diff line number Diff line
@@ -1211,8 +1211,8 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 
	ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);

	ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);



	ccr |= (rqc->dcctl << CC_SRCCCTRL_SHFT);

	ccr |= (rqc->scctl << CC_DSTCCTRL_SHFT);

	ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);

	ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);



	ccr |= (rqc->swap << CC_SWAP_SHFT);
@@ -1623,6 +1623,11 @@ static inline int _alloc_event(struct pl330_thread *thrd) 
	return -1;

}



static bool _chan_ns(const struct pl330_info *pi, int i)

{

	return pi->pcfg.irq_ns & (1 << i);

}



/* Upon success, returns IdentityToken for the

 * allocated channel, NULL otherwise.

 */
@@ -1647,7 +1652,8 @@ void *pl330_request_channel(const struct pl330_info *pi) 


	for (i = 0; i < chans; i++) {

		thrd = &pl330->channels[i];

		if (thrd->free) {

		if ((thrd->free) && (!_manager_ns(thrd) ||

					_chan_ns(pi, i))) {

			thrd->ev = _alloc_event(thrd);

			if (thrd->ev >= 0) {

				thrd->free = false;

arch/arm/include/asm/pmu.h

+0 −10
Original line number Diff line number Diff line
@@ -55,16 +55,6 @@ reserve_pmu(enum arm_pmu_type type); 
extern void

release_pmu(enum arm_pmu_type type);



/**

 * init_pmu() - Initialise the PMU.

 *

 * Initialise the system ready for PMU enabling. This should typically set the

 * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do

 * the actual hardware initialisation.

 */

extern int

init_pmu(enum arm_pmu_type type);



#else /* CONFIG_CPU_HAS_PMU */



#include <linux/err.h>

arch/arm/include/asm/topology.h

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ extern struct cputopo_arm cpu_topology[NR_CPUS]; 


void init_cpu_topology(void);

void store_cpu_topology(unsigned int cpuid);

const struct cpumask *cpu_coregroup_mask(unsigned int cpu);

const struct cpumask *cpu_coregroup_mask(int cpu);



#else