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Commit 39871d5a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Configure UCHE GMEM base address based on GMEM size"

parents d2f3780e 4286fbf4

drivers/gpu/msm/adreno-gpulist.h

+0 −22
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7ffffffe,

		.bus_width = 0,
@@ -48,7 +47,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7ffffffe,

		.bus_width = 16,
@@ -68,7 +66,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_base = 0,

		.gmem_size = (SZ_64K + SZ_32K),

		.busy_mask = 0x7ffffffe,

		.bus_width = 0,
@@ -192,7 +189,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
			ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -217,7 +213,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
			ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -282,7 +277,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 16,
@@ -301,7 +295,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 16,
@@ -378,7 +371,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { 
	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.busy_mask = 0xfffffffe,

		.bus_width = 16,
@@ -503,7 +495,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -585,7 +576,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { 
		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -603,7 +593,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -777,7 +766,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -876,7 +864,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -903,7 +890,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1031,7 +1017,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1121,7 +1106,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1201,7 +1185,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
			ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IFPC | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1232,7 +1215,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_LM | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1260,7 +1242,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1337,7 +1318,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1362,7 +1342,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.busy_mask = 0xfffffffe,

		.bus_width = 32,
@@ -1388,7 +1367,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
		.features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION |

			ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.busy_mask = 0xfffffffe,

		.bus_width = 32,

drivers/gpu/msm/adreno.c

+14 −3
Original line number Diff line number Diff line
@@ -829,6 +829,17 @@ static int adreno_identify_gpu(struct adreno_device *adreno_dev) 
		return -ENODEV;

	}



	/*

	 * Some GPUs needs UCHE GMEM base address to be minimum 0x100000

	 * and 1MB aligned. Configure UCHE GMEM base based on GMEM size

	 * and align it one 1MB. This needs to be done based on GMEM size

	 * because setting it to minimum value 0x100000 will result in RB

	 * and UCHE GMEM range overlap for GPUs with GMEM size >1MB.

	 */

	if (!adreno_is_a650_family(adreno_dev))

		adreno_dev->uche_gmem_base =

			ALIGN(adreno_dev->gpucore->gmem_size, SZ_1M);



	/*

	 * Initialize uninitialzed gpu registers, only needs to be done once

	 * Make all offsets that are not initialized to ADRENO_REG_UNUSED
@@ -2478,7 +2489,7 @@ static int adreno_prop_device_info(struct kgsl_device *device, 
		.device_id = device->id + 1,

		.chip_id = adreno_dev->chipid,

		.mmu_enabled = MMU_FEATURE(&device->mmu, KGSL_MMU_PAGED),

		.gmem_gpubaseaddr = adreno_dev->gpucore->gmem_base,

		.gmem_gpubaseaddr = 0,

		.gmem_sizebytes = adreno_dev->gpucore->gmem_size,

	};
@@ -2552,9 +2563,9 @@ static int adreno_prop_uche_gmem_addr(struct kgsl_device *device, 
		struct kgsl_device_getproperty *param)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	u64 vaddr = adreno_dev->gpucore->gmem_base;



	return copy_prop(param, &vaddr, sizeof(vaddr));

	return copy_prop(param, &adreno_dev->uche_gmem_base,

		sizeof(adreno_dev->uche_gmem_base));

}



static int adreno_prop_ucode_version(struct kgsl_device *device,

drivers/gpu/msm/adreno.h

+2 −2
Original line number Diff line number Diff line
@@ -352,7 +352,6 @@ struct adreno_reglist { 
 * @patchid: Match for the patch revision of the GPU

 * @features: Common adreno features supported by this core

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @busy_mask: mask to check if GPU is busy in RBBM_STATUS

 * @bus_width: Bytes transferred in 1 cycle
@@ -362,7 +361,6 @@ struct adreno_gpu_core { 
	unsigned int core, major, minor, patchid;

	unsigned long features;

	struct adreno_gpudev *gpudev;

	unsigned long gmem_base;

	size_t gmem_size;

	unsigned int busy_mask;

	u32 bus_width;
@@ -379,6 +377,7 @@ enum gpu_coresight_sources { 
 * @dev: Reference to struct kgsl_device

 * @priv: Holds the private flags specific to the adreno_device

 * @chipid: Chip ID specific to the GPU

 * @uche_gmem_base: Base address of GMEM for UCHE access

 * @cx_misc_len: Length of the CX MISC register block

 * @cx_misc_virt: Pointer where the CX MISC block is mapped

 * @rscc_base: Base physical address of the RSCC
@@ -463,6 +462,7 @@ struct adreno_device { 
	struct kgsl_device dev;    /* Must be first field in this struct */

	unsigned long priv;

	unsigned int chipid;

	u64 uche_gmem_base;

	unsigned long cx_dbgc_base;

	unsigned int cx_dbgc_len;

	void __iomem *cx_dbgc_virt;

drivers/gpu/msm/adreno_a5xx.c

+2 −2
Original line number Diff line number Diff line
@@ -1508,10 +1508,10 @@ static void a5xx_start(struct adreno_device *adreno_dev) 


	/* Program the GMEM VA range for the UCHE path */

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MIN_LO,

			adreno_dev->gpucore->gmem_base);

			adreno_dev->uche_gmem_base);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MAX_LO,

			adreno_dev->gpucore->gmem_base +

			adreno_dev->uche_gmem_base +

			adreno_dev->gpucore->gmem_size - 1);

	kgsl_regwrite(device, A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);

drivers/gpu/msm/adreno_a6xx.c

+6 −6
Original line number Diff line number Diff line
@@ -429,16 +429,16 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);



	/*

	 * Some A6xx targets no longer use a programmed GMEM base address

	 * so only write the registers if a non zero address is given

	 * in the GPU list

	 * Some A6xx targets no longer use a programmed UCHE GMEM base

	 * address so only write the registers if this address is

	 * non zero.

	 */

	if (adreno_dev->gpucore->gmem_base) {

	if (adreno_dev->uche_gmem_base) {

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_LO,

				adreno_dev->gpucore->gmem_base);

				adreno_dev->uche_gmem_base);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_LO,

				adreno_dev->gpucore->gmem_base +

				adreno_dev->uche_gmem_base +

				adreno_dev->gpucore->gmem_size - 1);

		kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0);

	}