Merge 231b07b4 on remote branch

Qualcomm Technologies, Inc. DPU KMS

Description:

Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates

sub-blocks like DPU display controller, DSI and DP interfaces etc.

The DPU display controller is found in SDM845 SoC.

MDSS:

Required properties:

- compatible: "qcom,sdm845-mdss"

- reg: physical base address and length of contoller's registers.

- reg-names: register region names. The following region is required:

  * "mdss"

- power-domains: a power domain consumer specifier according to

  Documentation/devicetree/bindings/power/power_domain.txt

- clocks: list of clock specifiers for clocks needed by the device.

- clock-names: device clock names, must be in same order as clocks property.

  The following clocks are required:

  * "iface"

  * "bus"

  * "core"

- interrupts: interrupt signal from MDSS.

- interrupt-controller: identifies the node as an interrupt controller.

- #interrupt-cells: specifies the number of cells needed to encode an interrupt

  source, should be 1.

- iommus: phandle of iommu device node.

- #address-cells: number of address cells for the MDSS children. Should be 1.

- #size-cells: Should be 1.

- ranges: parent bus address space is the same as the child bus address space.

Optional properties:

- assigned-clocks: list of clock specifiers for clocks needing rate assignment

- assigned-clock-rates: list of clock frequencies sorted in the same order as

  the assigned-clocks property.

MDP:

Required properties:

- compatible: "qcom,sdm845-dpu"

- reg: physical base address and length of controller's registers.

- reg-names : register region names. The following region is required:

  * "mdp"

  * "vbif"

- clocks: list of clock specifiers for clocks needed by the device.

- clock-names: device clock names, must be in same order as clocks property.

  The following clocks are required.

  * "bus"

  * "iface"

  * "core"

  * "vsync"

- interrupts: interrupt line from DPU to MDSS.

- ports: contains the list of output ports from DPU device. These ports connect

  to interfaces that are external to the DPU hardware, such as DSI, DP etc.

  Each output port contains an endpoint that describes how it is connected to an

  external interface. These are described by the standard properties documented

  here:

	Documentation/devicetree/bindings/graph.txt

	Documentation/devicetree/bindings/media/video-interfaces.txt

	Port 0 -> DPU_INTF1 (DSI1)

	Port 1 -> DPU_INTF2 (DSI2)

Optional properties:

- assigned-clocks: list of clock specifiers for clocks needing rate assignment

- assigned-clock-rates: list of clock frequencies sorted in the same order as

  the assigned-clocks property.

Example:

	mdss: mdss@ae00000 {

		compatible = "qcom,sdm845-mdss";

		reg = <0xae00000 0x1000>;

		reg-names = "mdss";

		power-domains = <&clock_dispcc 0>;

		clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;

		clock-names = "iface", "bus", "core";

		assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;

		assigned-clock-rates = <300000000>;

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <1>;

		iommus = <&apps_iommu 0>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0xae00000 0xb2008>;

		mdss_mdp: mdp@ae01000 {

			compatible = "qcom,sdm845-dpu";

			reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;

			reg-names = "mdp", "vbif";

			clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

				 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,

				 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,

				 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;

			clock-names = "iface", "bus", "core", "vsync";

			assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,

					  <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;

			assigned-clock-rates = <0 0 300000000 19200000>;

			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

			ports {

				#address-cells = <1>;

				#size-cells = <0>;

				port@0 {

					reg = <0>;

					dpu_intf1_out: endpoint {

						remote-endpoint = <&dsi0_in>;

					};

				};

				port@1 {

					reg = <1>;

					dpu_intf2_out: endpoint {

						remote-endpoint = <&dsi1_in>;

					};

				};

			};

		};

	};

Qualcomm Technologies Inc. adreno/snapdragon DSI output

DSI Controller:

Required properties:

- compatible:

  * "qcom,mdss-dsi-ctrl"

- reg: Physical base address and length of the registers of controller

- reg-names: The names of register regions. The following regions are required:

  * "dsi_ctrl"

- interrupts: The interrupt signal from the DSI block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks.

- clock-names: the following clocks are required:

  * "mdp_core"

  * "iface"

  * "bus"

  * "core_mmss"

  * "byte"

  * "pixel"

  * "core"

  For DSIv2, we need an additional clock:

   * "src"

  For DSI6G v2.0 onwards, we need also need the clock:

   * "byte_intf"

- assigned-clocks: Parents of "byte" and "pixel" for the given platform.

- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided

  by a DSI PHY block. See [1] for details on clock bindings.

- vdd-supply: phandle to vdd regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vdda-supply: phandle to vdda regulator device node

- phys: phandle to DSI PHY device node

- phy-names: the name of the corresponding PHY device

- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)

- ports: Contains 2 DSI controller ports as child nodes. Each port contains

  an endpoint subnode as defined in [2] and [3].

Optional properties:

- panel@0: Node of panel connected to this DSI controller.

  See files in [4] for each supported panel.

- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is

  driving a panel which needs 2 DSI links.

- qcom,master-dsi: Boolean value indicating if the DSI controller is driving

  the master link of the 2-DSI panel.

- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is

  driving a 2-DSI panel whose 2 links need receive command simultaneously.

- pinctrl-names: the pin control state names; should contain "default"

- pinctrl-0: the default pinctrl state (active)

- pinctrl-n: the "sleep" pinctrl state

- ports: contains DSI controller input and output ports as children, each

  containing one endpoint subnode.

  DSI Endpoint properties:

  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's

    input endpoint. For port@1, set to the MDP interface output. See [2] for

    device graph info.

  - data-lanes: this describes how the physical DSI data lanes are mapped

    to the logical lanes on the given platform. The value contained in

    index n describes what physical lane is mapped to the logical lane n

    (DATAn, where n lies between 0 and 3). The clock lane position is fixed

    and can't be changed. Hence, they aren't a part of the DT bindings. See

    [3] for more info on the data-lanes property.

    For example:

    data-lanes = <3 0 1 2>;

    The above mapping describes that the logical data lane DATA0 is mapped to

    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2

    to phys DATA1 and logic DATA3 to phys DATA2.

    There are only a limited number of physical to logical mappings possible:

    <0 1 2 3>

    <1 2 3 0>

    <2 3 0 1>

    <3 0 1 2>

    <0 3 2 1>

    <1 0 3 2>

    <2 1 0 3>

    <3 2 1 0>

DSI PHY:

Required properties:

- compatible: Could be the following

  * "qcom,dsi-phy-28nm-hpm"

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-28nm-8960"

  * "qcom,dsi-phy-14nm"

  * "qcom,dsi-phy-10nm"

- reg: Physical base address and length of the registers of PLL, PHY. Some

  revisions require the PHY regulator base address, whereas others require the

  PHY lane base address. See below for each PHY revision.

- reg-names: The names of register regions. The following regions are required:

  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

  For DSI 14nm and 10nm PHYs:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_lane"

- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating

  2 clocks: A byte clock (index 0), and a pixel clock (index 1).

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks. See [1] for details on clock bindings.

- clock-names: the following clocks are required:

  * "iface"

  For 28nm HPM/LP, 28nm 8960 PHYs:

- vddio-supply: phandle to vdd-io regulator device node

  For 20nm PHY:

- vddio-supply: phandle to vdd-io regulator device node

- vcca-supply: phandle to vcca regulator device node

  For 14nm PHY:

- vcca-supply: phandle to vcca regulator device node

  For 10nm PHY:

- vdds-supply: phandle to vdds regulator device node

Optional properties:

- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY

  regulator is wanted.

- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode

					panels in microseconds. Driver uses this number to adjust

					the clock rate according to the expected transfer time.

					Increasing this value would slow down the mdp processing

					and can result in slower performance.

					Decreasing this value can speed up the mdp processing,

					but this can also impact power consumption.

					As a rule this time should not be higher than the time

					that would be expected with the processing at the

					dsi link rate since anyways this would be the maximum

					transfer time that could be achieved.

					If ping pong split is enabled, this time should not be higher

					than two times the dsi link rate time.

					If the property is not specified, then the default value is 14000 us.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/graph.txt

[3] Documentation/devicetree/bindings/media/video-interfaces.txt

[4] Documentation/devicetree/bindings/display/panel/

Example:

	dsi0: dsi@fd922800 {

		compatible = "qcom,mdss-dsi-ctrl";

		qcom,dsi-host-index = <0>;

		interrupt-parent = <&mdp>;

		interrupts = <4 0>;

		reg-names = "dsi_ctrl";

		reg = <0xfd922800 0x200>;

		power-domains = <&mmcc MDSS_GDSC>;

		clock-names =

			"bus",

			"byte",

			"core",

			"core_mmss",

			"iface",

			"mdp_core",

			"pixel";

		clocks =

			<&mmcc MDSS_AXI_CLK>,

			<&mmcc MDSS_BYTE0_CLK>,

			<&mmcc MDSS_ESC0_CLK>,

			<&mmcc MMSS_MISC_AHB_CLK>,

			<&mmcc MDSS_AHB_CLK>,

			<&mmcc MDSS_MDP_CLK>,

			<&mmcc MDSS_PCLK0_CLK>;

		assigned-clocks =

				 <&mmcc BYTE0_CLK_SRC>,

				 <&mmcc PCLK0_CLK_SRC>;

		assigned-clock-parents =

				 <&dsi_phy0 0>,

				 <&dsi_phy0 1>;

		vdda-supply = <&pma8084_l2>;

		vdd-supply = <&pma8084_l22>;

		vddio-supply = <&pma8084_l12>;

		phys = <&dsi_phy0>;

		phy-names ="dsi-phy";

		qcom,dual-dsi-mode;

		qcom,master-dsi;

		qcom,sync-dual-dsi;

		qcom,mdss-mdp-transfer-time-us = <12000>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&dsi_active>;

		pinctrl-1 = <&dsi_suspend>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				dsi0_in: endpoint {

					remote-endpoint = <&mdp_intf1_out>;

				};

			};

			port@1 {

				reg = <1>;

				dsi0_out: endpoint {

					remote-endpoint = <&panel_in>;

					data-lanes = <0 1 2 3>;

				};

			};

		};

		panel: panel@0 {

			compatible = "sharp,lq101r1sx01";

			reg = <0>;

			link2 = <&secondary>;

			power-supply = <...>;

			backlight = <...>;

			port {

				panel_in: endpoint {

					remote-endpoint = <&dsi0_out>;

				};

			};

		};

	};

	dsi_phy0: dsi-phy@fd922a00 {

		compatible = "qcom,dsi-phy-28nm-hpm";

		qcom,dsi-phy-index = <0>;

		reg-names =

			"dsi_pll",

			"dsi_phy",

			"dsi_phy_regulator";

		reg =   <0xfd922a00 0xd4>,

			<0xfd922b00 0x2b0>,

			<0xfd922d80 0x7b>;

		clock-names = "iface";

		clocks = <&mmcc MDSS_AHB_CLK>;

		#clock-cells = <1>;

		vddio-supply = <&pma8084_l12>;

		qcom,dsi-phy-regulator-ldo-mode;

		qcom,panel-allow-phy-poweroff;

		qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;

		qcom,panel-force-clock-lane-hs;

	};

Qualcomm Technologies Inc. snapdragon eDP output

Required properties:

- compatible:

  * "qcom,mdss-edp"

- reg: Physical base address and length of the registers of controller and PLL

- reg-names: The names of register regions. The following regions are required:

  * "edp"

  * "pll_base"

- interrupts: The interrupt signal from the eDP block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core"

  * "iface"

  * "mdp_core"

  * "pixel"

  * "link"

- #clock-cells: The value should be 1.

- vdda-supply: phandle to vdda regulator device node

- lvl-vdd-supply: phandle to regulator device node which is used to supply power

  to HPD receiving chip

- panel-en-gpios: GPIO pin to supply power to panel.

- panel-hpd-gpios: GPIO pin used for eDP hpd.

Example:

	mdss_edp: qcom,mdss_edp@fd923400 {

			compatible = "qcom,mdss-edp";

			reg-names =

				"edp",

				"pll_base";

			reg =	<0xfd923400 0x700>,

				<0xfd923a00 0xd4>;

			interrupt-parent = <&mdss_mdp>;

			interrupts = <12 0>;

			power-domains = <&mmcc MDSS_GDSC>;

			clock-names =

				"core",

				"pixel",

				"iface",

				"link",

				"mdp_core";

			clocks =

				<&mmcc MDSS_EDPAUX_CLK>,

				<&mmcc MDSS_EDPPIXEL_CLK>,

				<&mmcc MDSS_AHB_CLK>,

				<&mmcc MDSS_EDPLINK_CLK>,

				<&mmcc MDSS_MDP_CLK>;

			#clock-cells = <1>;

			vdda-supply = <&pma8084_l12>;

			lvl-vdd-supply = <&lvl_vreg>;

			panel-en-gpios = <&tlmm 137 0>;

			panel-hpd-gpios = <&tlmm 103 0>;

	};

Qualcomm Technologies, Inc. adreno/snapdragon hdmi output

Required properties:

- compatible: one of the following

   * "qcom,hdmi-tx-8996"

   * "qcom,hdmi-tx-8994"

   * "qcom,hdmi-tx-8084"

   * "qcom,hdmi-tx-8974"

   * "qcom,hdmi-tx-8660"

   * "qcom,hdmi-tx-8960"

- reg: Physical base address and length of the controller's registers

- reg-names: "core_physical"

- interrupts: The interrupt signal from the hdmi block.

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- core-vdda-supply: phandle to supply regulator

- hdmi-mux-supply: phandle to mux regulator

- phys: the phandle for the HDMI PHY device

- phy-names: the name of the corresponding PHY device

Optional properties:

- hpd-gpios: hpd pin

- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin

- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin

- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin

- power-domains: reference to the power domain(s), if available.

- pinctrl-names: the pin control state names; should contain "default"

- pinctrl-0: the default pinctrl state (active)

- pinctrl-1: the "sleep" pinctrl state

HDMI PHY:

Required properties:

- compatible: Could be the following

  * "qcom,hdmi-phy-8660"

  * "qcom,hdmi-phy-8960"

  * "qcom,hdmi-phy-8974"

  * "qcom,hdmi-phy-8084"

  * "qcom,hdmi-phy-8996"

- #phy-cells: Number of cells in a PHY specifier; Should be 0.

- reg: Physical base address and length of the registers of the PHY sub blocks.

- reg-names: The names of register regions. The following regions are required:

  * "hdmi_phy"

  * "hdmi_pll"

  For HDMI PHY on msm8996, these additional register regions are required:

    * "hdmi_tx_l0"

    * "hdmi_tx_l1"

    * "hdmi_tx_l3"

    * "hdmi_tx_l4"

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- core-vdda-supply: phandle to vdda regulator device node

Example:

/ {

	...

	hdmi: hdmi@4a00000 {

		compatible = "qcom,hdmi-tx-8960";

		reg-names = "core_physical";

		reg = <0x04a00000 0x2f0>;

		interrupts = <GIC_SPI 79 0>;

		power-domains = <&mmcc MDSS_GDSC>;

		clock-names =

		    "core",

		    "master_iface",

		    "slave_iface";

		clocks =

		    <&mmcc HDMI_APP_CLK>,

		    <&mmcc HDMI_M_AHB_CLK>,

		    <&mmcc HDMI_S_AHB_CLK>;

		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;

		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;

		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;

		core-vdda-supply = <&pm8921_hdmi_mvs>;

		hdmi-mux-supply = <&ext_3p3v>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;

		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;

		phys = <&hdmi_phy>;

		phy-names = "hdmi_phy";

	};

	hdmi_phy: phy@4a00400 {

		compatible = "qcom,hdmi-phy-8960";

		reg-names = "hdmi_phy",

			    "hdmi_pll";

		reg = <0x4a00400 0x60>,

		      <0x4a00500 0x100>;

		#phy-cells = <0>;

		power-domains = <&mmcc MDSS_GDSC>;

		clock-names = "slave_iface";

		clocks = <&mmcc HDMI_S_AHB_CLK>;

		core-vdda-supply = <&pm8921_hdmi_mvs>;

	};

};

Qualcomm Technologies, Inc. adreno/snapdragon MDP4 display controller

Description:

This is the bindings documentation for the MDP4 display controller found in

SoCs like MSM8960, APQ8064 and MSM8660.

Required properties:

- compatible:

  * "qcom,mdp4" - mdp4

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the display controller.

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required.

  * "core_clk"

  * "iface_clk"

  * "bus_clk"

  * "lut_clk"

  * "hdmi_clk"

  * "tv_clk"

- ports: contains the list of output ports from MDP. These connect to interfaces

  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a

  special case since it is a part of the MDP block itself).

  Each output port contains an endpoint that describes how it is connected to an

  external interface. These are described by the standard properties documented

  here:

	Documentation/devicetree/bindings/graph.txt

	Documentation/devicetree/bindings/media/video-interfaces.txt

  The output port mappings are:

	Port 0 -> LCDC/LVDS

	Port 1 -> DSI1 Cmd/Video

	Port 2 -> DSI2 Cmd/Video

	Port 3 -> DTV

Optional properties:

- clock-names: the following clocks are optional:

  * "lut_clk"

Example:

/ {

	...

	hdmi: hdmi@4a00000 {

		...

		ports {

			...

			port@0 {

				reg = <0>;

				hdmi_in: endpoint {

					remote-endpoint = <&mdp_dtv_out>;

				};

			};

			...

		};

		...

	};

	...

	mdp: mdp@5100000 {

		compatible = "qcom,mdp4";

		reg = <0x05100000 0xf0000>;

		interrupts = <GIC_SPI 75 0>;

		clock-names =

		    "core_clk",

		    "iface_clk",

		    "lut_clk",

		    "hdmi_clk",

		    "tv_clk";

		clocks =

		    <&mmcc MDP_CLK>,

		    <&mmcc MDP_AHB_CLK>,

		    <&mmcc MDP_AXI_CLK>,

		    <&mmcc MDP_LUT_CLK>,

		    <&mmcc HDMI_TV_CLK>,

		    <&mmcc MDP_TV_CLK>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

				port@0 {

					reg = <0>;

					mdp_lvds_out: endpoint {

					};

				};

				port@1 {

					reg = <1>;

					mdp_dsi1_out: endpoint {

					};

				};

				port@2 {

					reg = <2>;

					mdp_dsi2_out: endpoint {

					};

				};

				port@3 {

					reg = <3>;

					mdp_dtv_out: endpoint {

						remote-endpoint = <&hdmi_in>;

					};

				};

		};

	};

};