Loading Documentation/devicetree/bindings/clock/keystone-pll.txt +4 −4 Original line number Diff line number Diff line Loading @@ -17,13 +17,14 @@ Required properties: - reg - pll control0 and pll multipler registers - reg-names : control and multiplier. The multiplier is applicable only for main pll clock - fixed-postdiv : fixed post divider value - fixed-postdiv : fixed post divider value. If absent, use clkod register bits for postdiv Example: mainpllclk: mainpllclk@2310110 { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclkmain>; clocks = <&refclksys>; reg = <0x02620350 4>, <0x02310110 4>; reg-names = "control", "multiplier"; fixed-postdiv = <2>; Loading @@ -32,11 +33,10 @@ Example: papllclk: papllclk@2620358 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclkmain>; clocks = <&refclkpass>; clock-output-names = "pa-pll-clk"; reg = <0x02620358 4>; reg-names = "control"; fixed-postdiv = <6>; }; Required properties: Loading drivers/clk/keystone/gate.c +8 −4 Original line number Diff line number Diff line Loading @@ -223,8 +223,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) data->domain_base = of_iomap(node, i); if (!data->domain_base) { pr_err("%s: domain ioremap failed\n", __func__); iounmap(data->control_base); goto out; goto unmap_ctrl; } of_property_read_u32(node, "domain-id", &data->domain_id); Loading @@ -237,16 +236,21 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) parent_name = of_clk_get_parent_name(node, 0); if (!parent_name) { pr_err("%s: Parent clock not found\n", __func__); goto out; goto unmap_domain; } clk = clk_register_psc(NULL, clk_name, parent_name, data, lock); if (clk) { if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); return; } pr_err("%s: error registering clk %s\n", __func__, node->name); unmap_domain: iounmap(data->domain_base); unmap_ctrl: iounmap(data->control_base); out: kfree(data); return; Loading drivers/clk/keystone/pll.c +20 −4 Original line number Diff line number Diff line Loading @@ -24,6 +24,8 @@ #define MAIN_PLLM_HIGH_MASK 0x7f000 #define PLLM_HIGH_SHIFT 6 #define PLLD_MASK 0x3f #define CLKOD_MASK 0x780000 #define CLKOD_SHIFT 19 /** * struct clk_pll_data - pll data structure Loading @@ -41,7 +43,10 @@ * @pllm_upper_mask: multiplier upper mask * @pllm_upper_shift: multiplier upper shift * @plld_mask: divider mask * @postdiv: Post divider * @clkod_mask: output divider mask * @clkod_shift: output divider shift * @plld_mask: divider mask * @postdiv: Fixed post divider */ struct clk_pll_data { bool has_pllctrl; Loading @@ -53,6 +58,8 @@ struct clk_pll_data { u32 pllm_upper_mask; u32 pllm_upper_shift; u32 plld_mask; u32 clkod_mask; u32 clkod_shift; u32 postdiv; }; Loading Loading @@ -90,6 +97,12 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, mult |= ((val & pll_data->pllm_upper_mask) >> pll_data->pllm_upper_shift); prediv = (val & pll_data->plld_mask); if (!pll_data->has_pllctrl) /* read post divider from od bits*/ postdiv = ((val & pll_data->clkod_mask) >> pll_data->clkod_shift) + 1; else postdiv = pll_data->postdiv; rate /= (prediv + 1); Loading Loading @@ -155,8 +168,11 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) } parent_name = of_clk_get_parent_name(node, 0); if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) goto out; if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { /* assume the PLL has output divider register bits */ pll_data->clkod_mask = CLKOD_MASK; pll_data->clkod_shift = CLKOD_SHIFT; } i = of_property_match_string(node, "reg-names", "control"); pll_data->pll_ctl0 = of_iomap(node, i); Loading Loading
Documentation/devicetree/bindings/clock/keystone-pll.txt +4 −4 Original line number Diff line number Diff line Loading @@ -17,13 +17,14 @@ Required properties: - reg - pll control0 and pll multipler registers - reg-names : control and multiplier. The multiplier is applicable only for main pll clock - fixed-postdiv : fixed post divider value - fixed-postdiv : fixed post divider value. If absent, use clkod register bits for postdiv Example: mainpllclk: mainpllclk@2310110 { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclkmain>; clocks = <&refclksys>; reg = <0x02620350 4>, <0x02310110 4>; reg-names = "control", "multiplier"; fixed-postdiv = <2>; Loading @@ -32,11 +33,10 @@ Example: papllclk: papllclk@2620358 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclkmain>; clocks = <&refclkpass>; clock-output-names = "pa-pll-clk"; reg = <0x02620358 4>; reg-names = "control"; fixed-postdiv = <6>; }; Required properties: Loading
drivers/clk/keystone/gate.c +8 −4 Original line number Diff line number Diff line Loading @@ -223,8 +223,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) data->domain_base = of_iomap(node, i); if (!data->domain_base) { pr_err("%s: domain ioremap failed\n", __func__); iounmap(data->control_base); goto out; goto unmap_ctrl; } of_property_read_u32(node, "domain-id", &data->domain_id); Loading @@ -237,16 +236,21 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock) parent_name = of_clk_get_parent_name(node, 0); if (!parent_name) { pr_err("%s: Parent clock not found\n", __func__); goto out; goto unmap_domain; } clk = clk_register_psc(NULL, clk_name, parent_name, data, lock); if (clk) { if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); return; } pr_err("%s: error registering clk %s\n", __func__, node->name); unmap_domain: iounmap(data->domain_base); unmap_ctrl: iounmap(data->control_base); out: kfree(data); return; Loading
drivers/clk/keystone/pll.c +20 −4 Original line number Diff line number Diff line Loading @@ -24,6 +24,8 @@ #define MAIN_PLLM_HIGH_MASK 0x7f000 #define PLLM_HIGH_SHIFT 6 #define PLLD_MASK 0x3f #define CLKOD_MASK 0x780000 #define CLKOD_SHIFT 19 /** * struct clk_pll_data - pll data structure Loading @@ -41,7 +43,10 @@ * @pllm_upper_mask: multiplier upper mask * @pllm_upper_shift: multiplier upper shift * @plld_mask: divider mask * @postdiv: Post divider * @clkod_mask: output divider mask * @clkod_shift: output divider shift * @plld_mask: divider mask * @postdiv: Fixed post divider */ struct clk_pll_data { bool has_pllctrl; Loading @@ -53,6 +58,8 @@ struct clk_pll_data { u32 pllm_upper_mask; u32 pllm_upper_shift; u32 plld_mask; u32 clkod_mask; u32 clkod_shift; u32 postdiv; }; Loading Loading @@ -90,6 +97,12 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, mult |= ((val & pll_data->pllm_upper_mask) >> pll_data->pllm_upper_shift); prediv = (val & pll_data->plld_mask); if (!pll_data->has_pllctrl) /* read post divider from od bits*/ postdiv = ((val & pll_data->clkod_mask) >> pll_data->clkod_shift) + 1; else postdiv = pll_data->postdiv; rate /= (prediv + 1); Loading Loading @@ -155,8 +168,11 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) } parent_name = of_clk_get_parent_name(node, 0); if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) goto out; if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { /* assume the PLL has output divider register bits */ pll_data->clkod_mask = CLKOD_MASK; pll_data->clkod_shift = CLKOD_SHIFT; } i = of_property_match_string(node, "reg-names", "control"); pll_data->pll_ctl0 = of_iomap(node, i); Loading