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Commit 38b7ca92 authored by Yishai Hadas's avatar Yishai Hadas Committed by Leon Romanovsky
Browse files

net/mlx5: Expose DEVX specification



This patch updates the mlx5_ifc structures and
command interface to support DEVX.

Signed-off-by: default avatarYishai Hadas <yishaih@mellanox.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@mellanox.com>
parent fc6c391a
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+4 −0
Original line number Diff line number Diff line
@@ -310,6 +310,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
	case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
	case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
	case MLX5_CMD_OP_FPGA_DESTROY_QP:
	case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
		return MLX5_CMD_STAT_OK;

	case MLX5_CMD_OP_QUERY_HCA_CAP:
@@ -427,6 +428,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
	case MLX5_CMD_OP_FPGA_MODIFY_QP:
	case MLX5_CMD_OP_FPGA_QUERY_QP:
	case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
	case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
		*status = MLX5_DRIVER_STATUS_ABORTED;
		*synd = MLX5_DRIVER_SYND;
		return -EIO;
@@ -599,6 +601,8 @@ const char *mlx5_command_str(int command)
	MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
	MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
	MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
	MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
	MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
	default: return "unknown command opcode";
	}
}
+3 −0
Original line number Diff line number Diff line
@@ -1071,6 +1071,9 @@ enum mlx5_qcam_feature_groups {
#define MLX5_CAP_GEN(mdev, cap) \
	MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)

#define MLX5_CAP_GEN_64(mdev, cap) \
	MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)

#define MLX5_CAP_GEN_MAX(mdev, cap) \
	MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)

+66 −1
Original line number Diff line number Diff line
@@ -75,6 +75,15 @@ enum {
	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
};

enum {
	MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
	MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
};

enum {
	MLX5_OBJ_TYPE_UCTX = 0x0004,
};

enum {
	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
@@ -242,6 +251,8 @@ enum {
	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
	MLX5_CMD_OP_MAX
};

@@ -1113,7 +1124,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
	u8         reserved_at_3f8[0x3];
	u8         log_max_current_uc_list[0x5];

	u8         reserved_at_400[0x80];
	u8         general_obj_types[0x40];

	u8         reserved_at_440[0x40];

	u8         reserved_at_480[0x3];
	u8         log_max_l2_table[0x5];
@@ -9115,4 +9128,56 @@ struct mlx5_ifc_dealloc_memic_out_bits {
	u8         reserved_at_40[0x40];
};

struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
	u8         opcode[0x10];
	u8         uid[0x10];

	u8         reserved_at_20[0x10];
	u8         obj_type[0x10];

	u8         obj_id[0x20];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
	u8         status[0x8];
	u8         reserved_at_8[0x18];

	u8         syndrome[0x20];

	u8         obj_id[0x20];

	u8         reserved_at_60[0x20];
};

struct mlx5_ifc_umem_bits {
	u8         modify_field_select[0x40];

	u8         reserved_at_40[0x5b];
	u8         log_page_size[0x5];

	u8         page_offset[0x20];

	u8         num_of_mtt[0x40];

	struct mlx5_ifc_mtt_bits  mtt[0];
};

struct mlx5_ifc_uctx_bits {
	u8         modify_field_select[0x40];

	u8         reserved_at_40[0x1c0];
};

struct mlx5_ifc_create_umem_in_bits {
	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
	struct mlx5_ifc_umem_bits                     umem;
};

struct mlx5_ifc_create_uctx_in_bits {
	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
	struct mlx5_ifc_uctx_bits                     uctx;
};

#endif /* MLX5_IFC_H */