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Commit 3875623c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-next-2017-01-23' of git://anongit.freedesktop.org/git/drm-misc into drm-next 

- cleanups&fixes for dw-hdmi bride driver (Laurent)
- updates for adv bridge driver (John Stultz) for nexus
- drm_crtc_from_index helper rollout (Shawn Guo)
- removing drm_framebuffer_unregister_private from drivers&core
- target_vblank (Andrey Grodzovsky)
- misc tiny stuff

* tag 'drm-misc-next-2017-01-23' of git://anongit.freedesktop.org/git/drm-misc: (49 commits)
  drm: qxl: Open code teardown function for qxl
  drm: qxl: Open code probing sequence for qxl
  drm/bridge: adv7511: Re-write the i2c address before EDID probing
  drm/bridge: adv7511: Reuse __adv7511_power_on/off() when probing EDID
  drm/bridge: adv7511: Rework adv7511_power_on/off() so they can be reused internally
  drm/bridge: adv7511: Enable HPD interrupts to support hotplug and improve monitor detection
  drm/bridge: adv7511: Switch to using drm_kms_helper_hotplug_event()
  drm/bridge: adv7511: Use work_struct to defer hotplug handing to out of irq context
  drm: vc4: use crtc helper drm_crtc_from_index()
  drm: tegra: use crtc helper drm_crtc_from_index()
  drm: nouveau: use crtc helper drm_crtc_from_index()
  drm: mediatek: use crtc helper drm_crtc_from_index()
  drm: kirin: use crtc helper drm_crtc_from_index()
  drm: exynos: use crtc helper drm_crtc_from_index()
  dt-bindings: display: dw-hdmi: Clean up DT bindings documentation
  drm: bridge: dw-hdmi: Assert SVSRET before resetting the PHY
  drm: bridge: dw-hdmi: Fix the name of the PHY reset macros
  drm: bridge: dw-hdmi: Define and use macros for PHY register addresses
  drm: bridge: dw-hdmi: Detect PHY type at runtime
  drm: bridge: dw-hdmi: Handle overflow workaround based on device version
  ...
parents a7e2641a 6f897f51

Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt

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Original line number Diff line number Diff line
@@ -38,10 +38,22 @@ The following input format properties are required except in "rgb 1x" and 
- adi,input-justification: The input bit justification ("left", "evenly",

  "right").



- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.

- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.

- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.

- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V

  on the chip.

- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is

  needed only for ADV7511.



The following properties are required for ADV7533:



- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should

  be one of 1, 2, 3 or 4.

- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.

- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.

- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be

  either 1.2V or 1.8V.



Optional properties:

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt

+33 −52
Original line number Diff line number Diff line 
DesignWare HDMI bridge bindings



Required properties:

- compatible: platform specific such as:

   * "snps,dw-hdmi-tx"

   * "fsl,imx6q-hdmi"

   * "fsl,imx6dl-hdmi"

   * "rockchip,rk3288-dw-hdmi"

- reg: Physical base address and length of the controller's registers.

- interrupts: The HDMI interrupt number

- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,

  as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,

  the clocks are soc specific, the clock-names should be "iahb", "isfr"

-port@[X]: SoC specific port nodes with endpoint definitions as defined

   in Documentation/devicetree/bindings/media/video-interfaces.txt,

   please refer to the SoC specific binding document:

    * Documentation/devicetree/bindings/display/imx/hdmi.txt

    * Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt



Optional properties

- reg-io-width: the width of the reg:1,4, default set to 1 if not present

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,

  if the property is omitted, a functionally reduced I2C bus

  controller on DW HDMI is probed

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"



Example:

	hdmi: hdmi@0120000 {

		compatible = "fsl,imx6q-hdmi";

		reg = <0x00120000 0x9000>;

		interrupts = <0 115 0x04>;

		gpr = <&gpr>;

		clocks = <&clks 123>, <&clks 124>;

		clock-names = "iahb", "isfr";

		ddc-i2c-bus = <&i2c2>;



		port@0 {

			reg = <0>;



			hdmi_mux_0: endpoint {

				remote-endpoint = <&ipu1_di0_hdmi>;

			};

		};



		port@1 {

			reg = <1>;



			hdmi_mux_1: endpoint {

				remote-endpoint = <&ipu1_di1_hdmi>;

			};

		};

	};
 
Synopsys DesignWare HDMI TX Encoder

===================================



This document defines device tree properties for the Synopsys DesignWare HDMI

TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding

specification by itself but is meant to be referenced by platform-specific

device tree bindings.



When referenced from platform device tree bindings the properties defined in

this document are defined as follows. The platform device tree bindings are

responsible for defining whether each property is required or optional.



- reg: Memory mapped base address and length of the DWC HDMI TX registers.



- reg-io-width: Width of the registers specified by the reg property. The

  value is expressed in bytes and must be equal to 1 or 4 if specified. The

  register width defaults to 1 if the property is not present.



- interrupts: Reference to the DWC HDMI TX interrupt.



- clocks: References to all the clocks specified in the clock-names property

  as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.



- clock-names: The DWC HDMI TX uses the following clocks.



  - "iahb" is the bus clock for either AHB and APB (mandatory).

  - "isfr" is the internal register configuration clock (mandatory).

  - "cec" is the HDMI CEC controller main clock (optional).



- ports: The connectivity of the DWC HDMI TX with the rest of the system is

  expressed in using ports as specified in the device graph bindings defined

  in Documentation/devicetree/bindings/graph.txt. The numbering of the ports

  is platform-specific.

Documentation/devicetree/bindings/display/imx/hdmi.txt

+29 −22
Original line number Diff line number Diff line 
Device-Tree bindings for HDMI Transmitter

Freescale i.MX6 DWC HDMI TX Encoder

===================================



HDMI Transmitter

================

The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP

with a companion PHY IP.



These DT bindings follow the Synopsys DWC HDMI TX bindings defined in

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the

following device-specific properties.



The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP

with accompanying PHY IP.



Required properties:

 - #address-cells : should be <1>

 - #size-cells : should be <0>

 - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".

 - gpr : should be <&gpr>.

   The phandle points to the iomuxc-gpr region containing the HDMI



- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".

- reg: See dw_hdmi.txt.

- interrupts: HDMI interrupt number

- clocks: See dw_hdmi.txt.

- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.

- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,

  numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.

  Each port shall have a single endpoint.

- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI

  multiplexer control register.

 - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described

   in Documentation/devicetree/bindings/clock/clock-bindings.txt and

   Documentation/devicetree/bindings/clock/imx6q-clock.txt.

 - port@[0-4]: Up to four port nodes with endpoint definitions as defined in

   Documentation/devicetree/bindings/media/video-interfaces.txt,

   corresponding to the four inputs to the HDMI multiplexer.



Optional properties:

 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

Optional properties



- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master

  or the functionally-reduced I2C master contained in the DWC HDMI. When

  connected to a system I2C master this property contains a phandle to that

  I2C master controller.





example:

Example:



	gpr: iomuxc-gpr@020e0000 {

		/* ... */

Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt

+29 −14
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Rockchip specific extensions to the Synopsys Designware HDMI

================================

Rockchip DWC HDMI TX Encoder

============================



The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP

with a companion PHY IP.



These DT bindings follow the Synopsys DWC HDMI TX bindings defined in

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the

following device-specific properties.





Required properties:

- compatible: "rockchip,rk3288-dw-hdmi";

- reg: Physical base address and length of the controller's registers.

- clocks: phandle to hdmi iahb and isfr clocks.

- clock-names: should be "iahb" "isfr"

- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.



- compatible: Shall contain "rockchip,rk3288-dw-hdmi".

- reg: See dw_hdmi.txt.

- reg-io-width: See dw_hdmi.txt. Shall be 4.

- interrupts: HDMI interrupt number

- ports: contain a port node with endpoint definitions as defined in

  Documentation/devicetree/bindings/media/video-interfaces.txt. For

  vopb,set the reg = <0> and set the reg = <1> for vopl.

- reg-io-width: the width of the reg:1,4, the value should be 4 on

  rk3288 platform

- clocks: See dw_hdmi.txt.

- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.

- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0

  corresponding to the video input of the controller. The port shall have two

  endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.

- rockchip,grf: Shall reference the GRF to mux vopl/vopb.



Optional properties

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"



- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master

  or the functionally-reduced I2C master contained in the DWC HDMI. When

  connected to a system I2C master this property contains a phandle to that

  I2C master controller.

- clock-names: See dw_hdmi.txt. The "cec" clock is optional.

- clock-names: May contain "cec" as defined in dw_hdmi.txt.





Example:



hdmi: hdmi@ff980000 {

	compatible = "rockchip,rk3288-dw-hdmi";

	reg = <0xff980000 0x20000>;

Documentation/gpu/drm-mm.rst

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@@ -470,3 +470,9 @@ DRM MM Range Allocator Function References 


.. kernel-doc:: include/drm/drm_mm.h

   :internal:



DRM Cache Handling

==================



.. kernel-doc:: drivers/gpu/drm/drm_cache.c

   :export: