Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 380cd582 authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
Browse files

MIPS: Loongson-3: Fast TLB refill handler 



Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.

[ralf@linux-mips.org: Resolve conflict.]

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12754/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 06e4814e

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -35,6 +35,9 @@ 
#ifndef cpu_has_htw

#define cpu_has_htw		(cpu_data[0].options & MIPS_CPU_HTW)

#endif

#ifndef cpu_has_ldpte

#define cpu_has_ldpte		(cpu_data[0].options & MIPS_CPU_LDPTE)

#endif

#ifndef cpu_has_rixiex

#define cpu_has_rixiex		(cpu_data[0].options & MIPS_CPU_RIXIEX)

#endif

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -402,6 +402,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_NAN_LEGACY	MBIT_ULL(38)	/* Legacy NaN implemented */

#define MIPS_CPU_NAN_2008	MBIT_ULL(39)	/* 2008 NaN implemented */

#define MIPS_CPU_VP		MBIT_ULL(40)	/* MIPSr6 Virtual Processors (multi-threading) */

#define MIPS_CPU_LDPTE		MBIT_ULL(41)	/* CPU has ldpte/lddir instructions */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+6 −0
Original line number Diff line number Diff line
@@ -1474,6 +1474,12 @@ do { \ 
#define read_c0_pwctl()		__read_32bit_c0_register($6, 6)

#define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)



#define read_c0_pgd()		__read_64bit_c0_register($9, 7)

#define write_c0_pgd(val)	__write_64bit_c0_register($9, 7, val)



#define read_c0_kpgd()		__read_64bit_c0_register($31, 7)

#define write_c0_kpgd(val)	__write_64bit_c0_register($31, 7, val)



/* Cavium OCTEON (cnMIPS) */

#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)

#define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)

arch/mips/include/asm/uasm.h

+2 −1
Original line number Diff line number Diff line
@@ -171,7 +171,8 @@ Ip_u2u1(_wsbh); 
Ip_u3u1u2(_xor);

Ip_u2u1u3(_xori);

Ip_u2u1(_yield);



Ip_u1u2(_ldpte);

Ip_u2u1u3(_lddir);



/* Handle labels. */

struct uasm_label {

arch/mips/include/uapi/asm/inst.h

+10 −0
Original line number Diff line number Diff line
@@ -203,6 +203,16 @@ enum mad_func { 
	nmadd_fp_op	= 0x0c, nmsub_fp_op	= 0x0e

};



/*

 * func field for page table walker (Loongson-3).

 */

enum ptw_func {

	lwdir_op = 0x00,

	lwpte_op = 0x01,

	lddir_op = 0x02,

	ldpte_op = 0x03,

};



/*

 * func field for special3 lx opcodes (Cavium Octeon).

 */