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Commit 37e541f7 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: sdm660: Add support for RPM controlled clocks"

parents f305dc62 4001006d

drivers/clk/qcom/clk-smd-rpm.c

+128 −1
Original line number Diff line number Diff line
@@ -960,12 +960,125 @@ static const struct rpm_smd_clk_desc rpm_clk_scuba = { 
	.num_clks = ARRAY_SIZE(scuba_clks),

};



/* sdm660 */

DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,

								19200000);

DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);

DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);

DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,

						QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,

						QCOM_SMD_RPM_MMXI_CLK, 0);

DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);

DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,

						QCOM_SMD_RPM_AGGR_CLK, 2);

DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,

						QCOM_SMD_RPM_MISC_CLK, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3);



DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,

							ln_bb_clk1_pin_ao, 0x1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,

							ln_bb_clk2_pin_ao, 0x2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,

							ln_bb_clk3_pin_ao, 0x3);

static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk,

	LONG_MAX);

static DEFINE_CLK_VOTER(aggre2_noc_msmbus_clk, aggre2_noc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(aggre2_noc_msmbus_a_clk, aggre2_noc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(aggre2_noc_usb_clk, aggre2_noc_clk, 19200000);

static DEFINE_CLK_VOTER(aggre2_noc_smmu_clk, aggre2_noc_clk, 1000);

static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo);





static struct clk_hw *sdm660_clks[] = {

	[RPM_SMD_XO_CLK_SRC]        = &sdm660_cxo.hw,

	[RPM_SMD_XO_A_CLK_SRC]      = &sdm660_cxo_a.hw,

	[RPM_SMD_SNOC_CLK]          = &sdm660_snoc_clk.hw,

	[RPM_SMD_SNOC_A_CLK]        = &sdm660_snoc_a_clk.hw,

	[RPM_SMD_BIMC_CLK]          = &sdm660_bimc_clk.hw,

	[RPM_SMD_BIMC_A_CLK]        = &sdm660_bimc_a_clk.hw,

	[RPM_SMD_QDSS_CLK]          = &sdm660_qdss_clk.hw,

	[RPM_SMD_QDSS_A_CLK]        = &sdm660_qdss_a_clk.hw,

	[RPM_SMD_RF_CLK1]           = &sdm660_rf_clk1.hw,

	[RPM_SMD_RF_CLK1_A]         = &sdm660_rf_clk1_ao.hw,

	[RPM_SMD_RF_CLK1_PIN]       = &sdm660_rf_clk1_pin.hw,

	[RPM_SMD_RF_CLK1_A_PIN]     = &sdm660_rf_clk1_ao_pin.hw,

	[RPM_SMD_AGGR2_NOC_CLK]     = &sdm660_aggre2_noc_clk.hw,

	[RPM_SMD_AGGR2_NOC_A_CLK]   = &sdm660_aggre2_noc_a_clk.hw,

	[RPM_SMD_CNOC_CLK]          = &sdm660_cnoc_clk.hw,

	[RPM_SMD_CNOC_A_CLK]        = &sdm660_cnoc_a_clk.hw,

	[RPM_SMD_IPA_CLK]           = &sdm660_ipa_clk.hw,

	[RPM_SMD_IPA_A_CLK]         = &sdm660_ipa_a_clk.hw,

	[RPM_SMD_CE1_CLK]           = &sdm660_ce1_clk.hw,

	[RPM_SMD_CE1_A_CLK]         = &sdm660_ce1_a_clk.hw,

	[RPM_SMD_DIV_CLK1]          = &sdm660_div_clk1.hw,

	[RPM_SMD_DIV_A_CLK1]       = &sdm660_div_clk1_ao.hw,

	[RPM_SMD_LN_BB_CLK1]        = &sdm660_ln_bb_clk1.hw,

	[RPM_SMD_LN_BB_CLK1_A]        = &sdm660_ln_bb_clk1_ao.hw,

	[RPM_SMD_LN_BB_CLK1_PIN]    = &sdm660_ln_bb_clk1_pin.hw,

	[RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_ao.hw,

	[RPM_SMD_LN_BB_CLK2]        = &sdm660_ln_bb_clk2.hw,

	[RPM_SMD_LN_BB_CLK2_A]     = &sdm660_ln_bb_clk2_ao.hw,

	[RPM_SMD_LN_BB_CLK2_PIN]    = &sdm660_ln_bb_clk2_pin.hw,

	[RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_ao.hw,

	[RPM_SMD_LN_BB_CLK3]        = &sdm660_ln_bb_clk3.hw,

	[RPM_SMD_LN_BB_CLK3_A]     = &sdm660_ln_bb_clk3_ao.hw,

	[RPM_SMD_LN_BB_CLK3_PIN]    = &sdm660_ln_bb_clk3_pin.hw,

	[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_ao.hw,

	[RPM_SMD_CNOC_PERIPH_CLK]   = &sdm660_cnoc_periph_clk.hw,

	[RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw,

	[RPM_SMD_MMSSNOC_AXI_CLK]       = &sdm660_mmssnoc_axi_clk.hw,

	[RPM_SMD_MMSSNOC_AXI_A_CLK]     = &sdm660_mmssnoc_axi_a_clk.hw,



	/* Voter Clocks */

	[BIMC_MSMBUS_CLK]       = &bimc_msmbus_clk.hw,

	[BIMC_MSMBUS_A_CLK]     = &bimc_msmbus_a_clk.hw,

	[CNOC_MSMBUS_CLK]       = &cnoc_msmbus_clk.hw,

	[CNOC_MSMBUS_A_CLK]     = &cnoc_msmbus_a_clk.hw,

	[MCD_CE1_CLK]           = &mcd_ce1_clk.hw,

	[QCEDEV_CE1_CLK]        = &qcedev_ce1_clk.hw,

	[QCRYPTO_CE1_CLK]       = &qcrypto_ce1_clk.hw,

	[QSEECOM_CE1_CLK]       = &qseecom_ce1_clk.hw,

	[SCM_CE1_CLK]           = &scm_ce1_clk.hw,

	[SNOC_MSMBUS_CLK]       = &snoc_msmbus_clk.hw,

	[SNOC_MSMBUS_A_CLK]     = &snoc_msmbus_a_clk.hw,

	[CXO_DWC3_CLK]          = &cxo_dwc3_clk.hw,

	[CXO_SMD_LPM_CLK]           = &cxo_lpm_clk.hw,

	[CXO_SMD_OTG_CLK]           = &cxo_otg_clk.hw,

	[CXO_SMD_PIL_LPASS_CLK]     = &cxo_pil_lpass_clk.hw,

	[CXO_SMD_PIL_CDSP_CLK]      = &cxo_pil_cdsp_clk.hw,

	[CNOC_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw,

	[AGGR2_NOC_MSMBUS_CLK]  = &aggre2_noc_msmbus_clk.hw,

	[AGGR2_NOC_MSMBUS_A_CLK] = &aggre2_noc_msmbus_a_clk.hw,

	[AGGR2_NOC_SMMU_CLK]    = &aggre2_noc_smmu_clk.hw,

	[AGGR2_NOC_USB_CLK]     = &aggre2_noc_usb_clk.hw,

};



static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {

	.clks = sdm660_clks,

	.num_rpm_clks = RPM_SMD_MMSSNOC_AXI_A_CLK,

	.num_clks = ARRAY_SIZE(sdm660_clks),

};



static const struct of_device_id rpm_smd_clk_match_table[] = {

	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },

	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },

	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },

	{ .compatible = "qcom,rpmcc-bengal", .data = &rpm_clk_bengal},

	{ .compatible = "qcom,rpmcc-scuba", .data = &rpm_clk_scuba},

	{ .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },

	{ }

};

MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
@@ -976,7 +1089,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) 
	struct clk *clk;

	struct rpm_cc *rcc;

	struct clk_onecell_data *data;

	int ret, is_bengal, is_scuba;

	int ret, is_bengal, is_scuba, is_sdm660;

	size_t num_clks, i;

	struct clk_hw **hw_clks;

	const struct rpm_smd_clk_desc *desc;
@@ -992,6 +1105,14 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) 
			return ret;

	}



	is_sdm660 = of_device_is_compatible(pdev->dev.of_node,

						"qcom,rpmcc-sdm660");

	if (is_sdm660) {

		ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX);

		if (ret < 0)

			return ret;

	}



	desc = of_device_get_match_data(&pdev->dev);

	if (!desc)

		return -EINVAL;
@@ -1069,6 +1190,12 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) 
		/* Hold an active set vote for the snoc_keepalive_a_clk */

		clk_set_rate(snoc_keepalive_a_clk.hw.clk, 19200000);

		clk_prepare_enable(snoc_keepalive_a_clk.hw.clk);

	} else if (is_sdm660) {

		clk_prepare_enable(sdm660_cxo_a.hw.clk);



		/* Hold an active set vote for the cnoc_periph resource */

		clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000);

		clk_prepare_enable(cnoc_periph_keepalive_a_clk.hw.clk);

	}



	dev_info(&pdev->dev, "Registered RPM clocks\n");

include/dt-bindings/clock/qcom,rpmcc.h

+86 −71
Original line number Diff line number Diff line
@@ -143,76 +143,91 @@ 
#define RPM_SMD_RF_CLK3_A_PIN			91

#define RPM_SMD_LN_BB_CLK1			92

#define RPM_SMD_LN_BB_CLK1_A			93

#define RPM_SMD_LN_BB_CLK2			94

#define RPM_SMD_LN_BB_CLK2_A			95

#define RPM_SMD_LN_BB_CLK3			96

#define RPM_SMD_LN_BB_CLK3_A			97

#define RPM_SMD_MMAXI_CLK			98

#define RPM_SMD_MMAXI_A_CLK			99

#define RPM_SMD_AGGR1_NOC_CLK			100

#define RPM_SMD_AGGR1_NOC_A_CLK			101

#define RPM_SMD_AGGR2_NOC_CLK			102

#define RPM_SMD_AGGR2_NOC_A_CLK			103

#define PNOC_MSMBUS_CLK				104

#define PNOC_MSMBUS_A_CLK			105

#define PNOC_KEEPALIVE_A_CLK			106

#define SNOC_MSMBUS_CLK				107

#define SNOC_MSMBUS_A_CLK			108

#define BIMC_MSMBUS_CLK				109

#define BIMC_MSMBUS_A_CLK			110

#define PNOC_USB_CLK				111

#define PNOC_USB_A_CLK				112

#define SNOC_USB_CLK				113

#define SNOC_USB_A_CLK				114

#define BIMC_USB_CLK				115

#define BIMC_USB_A_CLK				116

#define SNOC_WCNSS_A_CLK			117

#define BIMC_WCNSS_A_CLK			118

#define MCD_CE1_CLK				119

#define QCEDEV_CE1_CLK				120

#define QCRYPTO_CE1_CLK				121

#define QSEECOM_CE1_CLK				122

#define SCM_CE1_CLK				123

#define CXO_SMD_OTG_CLK				124

#define CXO_SMD_LPM_CLK				125

#define CXO_SMD_PIL_PRONTO_CLK			126

#define CXO_SMD_PIL_MSS_CLK			127

#define CXO_SMD_WLAN_CLK			128

#define CXO_SMD_PIL_LPASS_CLK			129

#define CXO_SMD_PIL_CDSP_CLK			130

#define CNOC_MSMBUS_CLK				131

#define CNOC_MSMBUS_A_CLK			132

#define CNOC_KEEPALIVE_A_CLK			133

#define SNOC_KEEPALIVE_A_CLK			134

#define CPP_MMNRT_MSMBUS_CLK			135

#define CPP_MMNRT_MSMBUS_A_CLK			136

#define JPEG_MMNRT_MSMBUS_CLK			137

#define JPEG_MMNRT_MSMBUS_A_CLK			138

#define VENUS_MMNRT_MSMBUS_CLK			139

#define VENUS_MMNRT_MSMBUS_A_CLK		140

#define ARM9_MMNRT_MSMBUS_CLK			141

#define ARM9_MMNRT_MSMBUS_A_CLK			142

#define MDP_MMRT_MSMBUS_CLK			143

#define MDP_MMRT_MSMBUS_A_CLK			144

#define VFE_MMRT_MSMBUS_CLK			145

#define VFE_MMRT_MSMBUS_A_CLK			146

#define QUP0_MSMBUS_SNOC_PERIPH_CLK		147

#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK		148

#define QUP1_MSMBUS_SNOC_PERIPH_CLK		149

#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK		150

#define QUP2_MSMBUS_SNOC_PERIPH_CLK             151

#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK           152

#define DAP_MSMBUS_SNOC_PERIPH_CLK		153

#define DAP_MSMBUS_SNOC_PERIPH_A_CLK		154

#define SDC1_MSMBUS_SNOC_PERIPH_CLK		155

#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK		156

#define SDC2_MSMBUS_SNOC_PERIPH_CLK		157

#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK		158

#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK		159

#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK		160

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK		161

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK	162

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK		163

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK	164

#define RPM_SMD_LN_BB_CLK1_PIN			94

#define RPM_SMD_LN_BB_CLK1_A_PIN		95

#define RPM_SMD_LN_BB_CLK2			96

#define RPM_SMD_LN_BB_CLK2_A			97

#define RPM_SMD_LN_BB_CLK2_PIN			98

#define RPM_SMD_LN_BB_CLK2_A_PIN		99

#define RPM_SMD_LN_BB_CLK3			100

#define RPM_SMD_LN_BB_CLK3_A		     101

#define RPM_SMD_LN_BB_CLK3_PIN		     102

#define RPM_SMD_LN_BB_CLK3_A_PIN	     103

#define RPM_SMD_MMAXI_CLK			     104

#define RPM_SMD_MMAXI_A_CLK			     105

#define RPM_SMD_AGGR1_NOC_CLK		     106

#define RPM_SMD_AGGR1_NOC_A_CLK		     107

#define RPM_SMD_AGGR2_NOC_CLK		     108

#define RPM_SMD_AGGR2_NOC_A_CLK		     109

#define RPM_SMD_CNOC_PERIPH_CLK		     110

#define RPM_SMD_CNOC_PERIPH_A_CLK	     111

#define RPM_SMD_MMSSNOC_AXI_CLK		     112

#define RPM_SMD_MMSSNOC_AXI_A_CLK	     113

#define PNOC_MSMBUS_CLK				     114

#define PNOC_MSMBUS_A_CLK			     115

#define PNOC_KEEPALIVE_A_CLK		     116

#define SNOC_MSMBUS_CLK				     117

#define SNOC_MSMBUS_A_CLK			     118

#define BIMC_MSMBUS_CLK				     119

#define BIMC_MSMBUS_A_CLK			     120

#define PNOC_USB_CLK				     121

#define PNOC_USB_A_CLK				     122

#define SNOC_USB_CLK				     123

#define SNOC_USB_A_CLK				     124

#define BIMC_USB_CLK				     125

#define BIMC_USB_A_CLK				     126

#define SNOC_WCNSS_A_CLK			     127

#define BIMC_WCNSS_A_CLK			     128

#define MCD_CE1_CLK				         129

#define QCEDEV_CE1_CLK				     130

#define QCRYPTO_CE1_CLK				     131

#define QSEECOM_CE1_CLK				     132

#define SCM_CE1_CLK				         133

#define CXO_SMD_OTG_CLK				     134

#define CXO_SMD_LPM_CLK				     135

#define CXO_SMD_PIL_PRONTO_CLK		     136

#define CXO_SMD_PIL_MSS_CLK			     137

#define CXO_SMD_WLAN_CLK			     138

#define CXO_SMD_PIL_LPASS_CLK		     139

#define CXO_SMD_PIL_CDSP_CLK		     140

#define CXO_DWC3_CLK				     141

#define CNOC_MSMBUS_CLK				     142

#define CNOC_MSMBUS_A_CLK			     143

#define CNOC_KEEPALIVE_A_CLK		     144

#define SNOC_KEEPALIVE_A_CLK			 145

#define CPP_MMNRT_MSMBUS_CLK			 146

#define CPP_MMNRT_MSMBUS_A_CLK			 147

#define JPEG_MMNRT_MSMBUS_CLK			 148

#define JPEG_MMNRT_MSMBUS_A_CLK			 149

#define VENUS_MMNRT_MSMBUS_CLK			 150

#define VENUS_MMNRT_MSMBUS_A_CLK		 151

#define ARM9_MMNRT_MSMBUS_CLK			 152

#define ARM9_MMNRT_MSMBUS_A_CLK			 153

#define MDP_MMRT_MSMBUS_CLK			     154

#define MDP_MMRT_MSMBUS_A_CLK			 155

#define VFE_MMRT_MSMBUS_CLK			     156

#define VFE_MMRT_MSMBUS_A_CLK			 157

#define QUP0_MSMBUS_SNOC_PERIPH_CLK			158

#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK	    159

#define QUP1_MSMBUS_SNOC_PERIPH_CLK		    160

#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK	    161

#define QUP2_MSMBUS_SNOC_PERIPH_CLK         162

#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK       163

#define DAP_MSMBUS_SNOC_PERIPH_CLK		    164

#define DAP_MSMBUS_SNOC_PERIPH_A_CLK	    165

#define SDC1_MSMBUS_SNOC_PERIPH_CLK		    166

#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK	    167

#define SDC2_MSMBUS_SNOC_PERIPH_CLK		    168

#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK	    169

#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK	    170

#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK		171

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK		172

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK	173

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK		174

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK	175

#define AGGR2_NOC_MSMBUS_CLK		        176

#define AGGR2_NOC_MSMBUS_A_CLK		        177

#define AGGR2_NOC_SMMU_CLK			        178

#define AGGR2_NOC_USB_CLK			        179



#endif