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Commit 37c1d94f authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Emit SRM after the MSG_FBC_REND_STATE LRI 



The spec tells us that we need to emit an SRM after the LRI
to MSG_FBC_REND_STATE.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 9688ecad

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -235,6 +235,7 @@ 
 */

#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)

#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)

#define  MI_SRM_LRM_GLOBAL_GTT		(1<<22)

#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */

#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)

#define   MI_INVALIDATE_TLB		(1<<18)

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −2
Original line number Diff line number Diff line
@@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) 
	if (!ring->fbc_dirty)

		return 0;



	ret = intel_ring_begin(ring, 4);

	ret = intel_ring_begin(ring, 6);

	if (ret)

		return ret;

	intel_ring_emit(ring, MI_NOOP);

	/* WaFbcNukeOn3DBlt:ivb/hsw */

	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

	intel_ring_emit(ring, MSG_FBC_REND_STATE);

	intel_ring_emit(ring, value);

	intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);

	intel_ring_emit(ring, MSG_FBC_REND_STATE);

	intel_ring_emit(ring, ring->scratch.gtt_offset + 256);

	intel_ring_advance(ring);



	ring->fbc_dirty = false;