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Commit 379b5441 authored by Zach Brown's avatar Zach Brown Committed by Sam Ravnborg
Browse files

x86: align per-cpu section to configured cache bytes 



This matches the fix for a bug seen on x86-64.  Test booted on old hardware
that had 32 byte cachelines to begin with.

Signed-off-by: default avatarZach Brown <zach.brown@oracle.com>
Signed-off-by: default avatarSam Ravnborg <sam@ravnborg.org>
parent 8e70c458

arch/i386/kernel/vmlinux.lds.S

+2 −1
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <asm-generic/vmlinux.lds.h>

#include <asm/thread_info.h>

#include <asm/page.h>

#include <asm/cache.h>



OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")

OUTPUT_ARCH(i386)
@@ -115,7 +116,7 @@ SECTIONS 
  __initramfs_start = .;

  .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { *(.init.ramfs) }

  __initramfs_end = .;

  . = ALIGN(32);

  . = ALIGN(L1_CACHE_BYTES);

  __per_cpu_start = .;

  .data.percpu  : AT(ADDR(.data.percpu) - LOAD_OFFSET) { *(.data.percpu) }

  __per_cpu_end = .;