Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 368400e2 authored by Christoffer Dall's avatar Christoffer Dall Committed by Sudeep Holla
Browse files

ARM: dts: vexpress: Support GICC_DIR operations 



The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT.  Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt
deactivation.

Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
[sudeep.holla@arm.com: included same fix for tc1 platform too]
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 7ce7d89f

arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ 
		#address-cells = <0>;

		interrupt-controller;

		reg = <0 0x2c001000 0 0x1000>,

		      <0 0x2c002000 0 0x1000>,

		      <0 0x2c002000 0 0x2000>,

		      <0 0x2c004000 0 0x2000>,

		      <0 0x2c006000 0 0x2000>;

		interrupts = <1 9 0xf04>;

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

+1 −1
Original line number Diff line number Diff line
@@ -131,7 +131,7 @@ 
		#address-cells = <0>;

		interrupt-controller;

		reg = <0 0x2c001000 0 0x1000>,

		      <0 0x2c002000 0 0x1000>,

		      <0 0x2c002000 0 0x2000>,

		      <0 0x2c004000 0 0x2000>,

		      <0 0x2c006000 0 0x2000>;

		interrupts = <1 9 0xf04>;