Commit 36383a08 authored May 23, 2018 by Simon Guo Committed by Paul Mackerras Jun 01, 2018

KVM: PPC: Book3S PR: Avoid changing TS bits when exiting guest



PR KVM host usually runs with TM enabled in its host MSR value, and
with non-transactional TS value.

When a guest with TM active traps into PR KVM host, the rfid at the
tail of kvmppc_interrupt_pr() will try to switch TS bits from
S0 (Suspended & TM disabled) to N1 (Non-transactional & TM enabled).

That will leads to TM Bad Thing interrupt.

This patch manually sets target TS bits unchanged to avoid this
exception.

Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

parent 401a89e9

arch/powerpc/kvm/book3s_segment.S

+13 −0

Original line number	Diff line number	Diff line
		@@ -383,6 +383,19 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
		*/

		PPC_LL r6, HSTATE_HOST_MSR(r13)
		#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
		/*
		* We don't want to change MSR[TS] bits via rfi here.
		* The actual TM handling logic will be in host with
		* recovered DR/IR bits after HSTATE_VMHANDLER.
		* And MSR_TM can be enabled in HOST_MSR so rfid may
		* not suppress this change and can lead to exception.
		* Manually set MSR to prevent TS state change here.
		*/
		mfmsr r7
		rldicl r7, r7, 64 - MSR_TS_S_LG, 62
		rldimi r6, r7, MSR_TS_S_LG, 63 - MSR_TS_T_LG
		#endif
		PPC_LL r8, HSTATE_VMHANDLER(r13)

		#ifdef CONFIG_PPC64