Merge branch 'drm-intel-fixes' into drm-intel-next (3619df03) · Commits · e / devices / android_kernel_fairphone_FP4

MAINTAINERS

+1 −1

Original line number	Diff line number	Diff line
		@@ -2080,7 +2080,7 @@ F: include/drm/

		INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
		M: Chris Wilson <chris@chris-wilson.co.uk>
		L: intel-gfx@lists.freedesktop.org
		L: intel-gfx@lists.freedesktop.org (subscribers-only)
		L: dri-devel@lists.freedesktop.org
		T: git git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git
		S: Supported

drivers/gpu/drm/i915/i915_gem.c

+16 −36

Original line number	Diff line number	Diff line
		@@ -35,8 +35,7 @@
		#include <linux/swap.h>
		#include <linux/pci.h>

		static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj,
		struct intel_ring_buffer *pipelined);
		static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
		static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
		static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
		static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
		@@ -2552,10 +2551,7 @@ i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj,
		* before clearing the fence.
		*/
		if (obj->fenced_gpu_access) {
		ret = i915_gem_object_flush_gpu_write_domain(obj, NULL);
		if (ret)
		return ret;

		i915_gem_object_flush_gpu_write_domain(obj);
		obj->fenced_gpu_access = false;
		}

		@@ -2735,23 +2731,17 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj)
		}

		/** Flushes any GPU write domain for the object if it's dirty. */
		static int
		i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj,
		struct intel_ring_buffer *pipelined)
		static void
		i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
		{
		struct drm_device *dev = obj->base.dev;

		if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
		return 0;
		return;

		/* Queue the GPU write cache flushing we need. */
		i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
		BUG_ON(obj->base.write_domain);

		if (pipelined && pipelined == obj->ring)
		return 0;

		return i915_gem_object_wait_rendering(obj, true);
		}

		/** Flushes the GTT write domain for the object if it's dirty. */
		@@ -2812,17 +2802,12 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
		if (obj->gtt_space == NULL)
		return -EINVAL;

		ret = i915_gem_object_flush_gpu_write_domain(obj, NULL);
		if (ret != 0)
		return ret;

		i915_gem_object_flush_cpu_write_domain(obj);

		if (write) {
		i915_gem_object_flush_gpu_write_domain(obj);
		ret = i915_gem_object_wait_rendering(obj, true);
		if (ret)
		return ret;
		}

		i915_gem_object_flush_cpu_write_domain(obj);

		old_write_domain = obj->base.write_domain;
		old_read_domains = obj->base.read_domains;
		@@ -2860,9 +2845,7 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
		if (obj->gtt_space == NULL)
		return -EINVAL;

		ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
		if (ret)
		return ret;
		i915_gem_object_flush_gpu_write_domain(obj);

		/* Currently, we are always called from an non-interruptible context. */
		if (!pipelined) {
		@@ -2909,8 +2892,9 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
		uint32_t old_write_domain, old_read_domains;
		int ret;

		ret = i915_gem_object_flush_gpu_write_domain(obj, false);
		if (ret != 0)
		i915_gem_object_flush_gpu_write_domain(obj);
		ret = i915_gem_object_wait_rendering(obj, true);
		if (ret)
		return ret;

		i915_gem_object_flush_gtt_write_domain(obj);
		@@ -2920,12 +2904,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
		*/
		i915_gem_object_set_to_full_cpu_read_domain(obj);

		if (write) {
		ret = i915_gem_object_wait_rendering(obj, true);
		if (ret)
		return ret;
		}

		old_write_domain = obj->base.write_domain;
		old_read_domains = obj->base.read_domains;

		@@ -3009,9 +2987,11 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
		if (offset == 0 && size == obj->base.size)
		return i915_gem_object_set_to_cpu_domain(obj, 0);

		ret = i915_gem_object_flush_gpu_write_domain(obj, false);
		if (ret != 0)
		i915_gem_object_flush_gpu_write_domain(obj);
		ret = i915_gem_object_wait_rendering(obj, true);
		if (ret)
		return ret;

		i915_gem_object_flush_gtt_write_domain(obj);

		/* If we're already fully in the CPU read domain, we're done. */

drivers/gpu/drm/i915/intel_sdvo.c

+11 −48

Original line number	Diff line number	Diff line
		@@ -1296,55 +1296,14 @@ intel_sdvo_get_edid(struct drm_connector *connector)
		return drm_get_edid(connector, &sdvo->ddc);
		}

		static struct drm_connector *
		intel_find_analog_connector(struct drm_device *dev)
		{
		struct drm_connector *connector;
		struct intel_sdvo *encoder;

		list_for_each_entry(encoder,
		&dev->mode_config.encoder_list,
		base.base.head) {
		if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
		list_for_each_entry(connector,
		&dev->mode_config.connector_list,
		head) {
		if (&encoder->base ==
		intel_attached_encoder(connector))
		return connector;
		}
		}
		}

		return NULL;
		}

		static int
		intel_analog_is_connected(struct drm_device *dev)
		{
		struct drm_connector *analog_connector;

		analog_connector = intel_find_analog_connector(dev);
		if (!analog_connector)
		return false;

		if (analog_connector->funcs->detect(analog_connector, false) ==
		connector_status_disconnected)
		return false;

		return true;
		}

		/* Mac mini hack -- use the same DDC as the analog connector */
		static struct edid *
		intel_sdvo_get_analog_edid(struct drm_connector *connector)
		{
		struct drm_i915_private *dev_priv = connector->dev->dev_private;

		if (!intel_analog_is_connected(connector->dev))
		return NULL;

		return drm_get_edid(connector, &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
		return drm_get_edid(connector,
		&dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
		}

		enum drm_connector_status
		@@ -1418,10 +1377,12 @@ intel_sdvo_detect(struct drm_connector *connector, bool force)
		if (!intel_sdvo_write_cmd(intel_sdvo,
		SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
		return connector_status_unknown;
		if (intel_sdvo->is_tv) {
		/* add 30ms delay when the output type is SDVO-TV */

		/* add 30ms delay when the output type might be TV */
		if (intel_sdvo->caps.output_flags &
		(SDVO_OUTPUT_SVID0 \| SDVO_OUTPUT_CVBS0))
		mdelay(30);
		}

		if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
		return connector_status_unknown;

		@@ -1475,8 +1436,10 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
		edid = intel_sdvo_get_analog_edid(connector);

		if (edid != NULL) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
		drm_mode_connector_update_edid_property(connector, edid);
		drm_add_edid_modes(connector, edid);
		}
		connector->display_info.raw_edid = NULL;
		kfree(edid);
		}