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Commit 3609e7ba authored by Kieran Bingham's avatar Kieran Bingham Committed by Mauro Carvalho Chehab
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media: v4l: vsp1: Provide UDS register updates 



Provide register definitions required for UDS phase and partition
algorithm support. The registers and bits defined here are available on
Gen3 hardware only.

Signed-off-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarHans Verkuil <hansverk@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent 40650268

drivers/media/platform/vsp1/vsp1_regs.h

+14 −0
Original line number Diff line number Diff line
@@ -388,6 +388,7 @@ 
#define VI6_UDS_CTRL_NE_RCR		(1 << 18)

#define VI6_UDS_CTRL_NE_GY		(1 << 17)

#define VI6_UDS_CTRL_NE_BCB		(1 << 16)

#define VI6_UDS_CTRL_AMDSLH		(1 << 2)

#define VI6_UDS_CTRL_TDIPC		(1 << 1)



#define VI6_UDS_SCALE			0x2304
@@ -420,11 +421,24 @@ 
#define VI6_UDS_PASS_BWIDTH_V_MASK	(0x7f << 0)

#define VI6_UDS_PASS_BWIDTH_V_SHIFT	0



#define VI6_UDS_HPHASE			0x2314

#define VI6_UDS_HPHASE_HSTP_MASK	(0xfff << 16)

#define VI6_UDS_HPHASE_HSTP_SHIFT	16

#define VI6_UDS_HPHASE_HEDP_MASK	(0xfff << 0)

#define VI6_UDS_HPHASE_HEDP_SHIFT	0



#define VI6_UDS_IPC			0x2318

#define VI6_UDS_IPC_FIELD		(1 << 27)

#define VI6_UDS_IPC_VEDP_MASK		(0xfff << 0)

#define VI6_UDS_IPC_VEDP_SHIFT		0



#define VI6_UDS_HSZCLIP			0x231c

#define VI6_UDS_HSZCLIP_HCEN		(1 << 28)

#define VI6_UDS_HSZCLIP_HCL_OFST_MASK	(0xff << 16)

#define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT	16

#define VI6_UDS_HSZCLIP_HCL_SIZE_MASK	(0x1fff << 0)

#define VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT	0



#define VI6_UDS_CLIP_SIZE		0x2324

#define VI6_UDS_CLIP_SIZE_HSIZE_MASK	(0x1fff << 16)

#define VI6_UDS_CLIP_SIZE_HSIZE_SHIFT	16