Merge "disp: msm: sde: fix cwb, dp and wb tear down sequence" (35882843) · Commits · e / devices / android_kernel_fairphone_FP4

msm/sde/sde_encoder.c

+20 −19

Original line number	Diff line number	Diff line
		@@ -3381,10 +3381,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
		{
		struct sde_encoder_virt *sde_enc;

		if (wb_enc) {
		if (sde_encoder_helper_reset_mixers(phys_enc, NULL))
		return;
		phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
		sde_encoder_helper_reset_mixers(phys_enc, NULL);

		if (wb_enc) {
		if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
		wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
		false, phys_enc->hw_pp->idx);
		@@ -4180,34 +4180,22 @@ void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
		struct sde_encoder_phys *phys;
		unsigned int i;
		struct sde_hw_ctl *ctl;
		struct msm_display_info *disp_info;

		if (!drm_enc) {
		SDE_ERROR("invalid encoder\n");
		return;
		}
		sde_enc = to_sde_encoder_virt(drm_enc);
		disp_info = &sde_enc->disp_info;

		for (i = 0; i < sde_enc->num_phys_encs; i++) {
		phys = sde_enc->phys_encs[i];

		if (phys && phys->hw_ctl) {
		if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
		sde_encoder_check_curr_mode(drm_enc,
		MSM_DISPLAY_CMD_MODE)) {
		ctl = phys->hw_ctl;
		/*
		* avoid clearing the pending flush during the first
		* frame update after idle power collpase as the
		* restore path would have updated the pending flush
		*/
		if (!sde_enc->idle_pc_restore &&
		ctl->ops.clear_pending_flush)
		ctl->ops.clear_pending_flush(ctl);

		if (ctl->ops.trigger_pending)
		/* update only for command mode primary ctl */
		if ((phys == sde_enc->cur_master) &&
		(sde_encoder_check_curr_mode(drm_enc,
		MSM_DISPLAY_CMD_MODE))
		&& ctl->ops.trigger_pending)
		ctl->ops.trigger_pending(ctl);
		}
		}
		@@ -4933,6 +4921,7 @@ void sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
		struct sde_encoder_virt *sde_enc;
		struct sde_encoder_phys *phys;
		int i;
		struct sde_hw_ctl *ctl;

		if (!drm_enc) {
		SDE_ERROR("invalid encoder\n");
		@@ -4944,6 +4933,18 @@ void sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
		phys = sde_enc->phys_encs[i];
		if (phys && phys->ops.prepare_commit)
		phys->ops.prepare_commit(phys);

		if (phys && phys->hw_ctl) {
		ctl = phys->hw_ctl;
		/*
		* avoid clearing the pending flush during the first
		* frame update after idle power collpase as the
		* restore path would have updated the pending flush
		*/
		if (!sde_enc->idle_pc_restore &&
		ctl->ops.clear_pending_flush)
		ctl->ops.clear_pending_flush(ctl);
		}
		}
		}

msm/sde/sde_encoder_phys_wb.c

+5 −4

Original line number	Diff line number	Diff line
		@@ -500,7 +500,7 @@ static void _sde_encoder_phys_wb_setup_cwb(struct sde_encoder_phys *phys_enc,
		hw_wb->ops.bind_pingpong_blk(hw_wb, enable, hw_pp->idx);

		if (hw_ctl->ops.update_cwb_cfg) {
		hw_ctl->ops.update_cwb_cfg(hw_ctl, &intf_cfg);
		hw_ctl->ops.update_cwb_cfg(hw_ctl, &intf_cfg, enable);
		SDE_DEBUG("in CWB mode on CTL_%d PP-%d merge3d:%d\n",
		hw_ctl->idx - CTL_0,
		hw_pp->idx - PINGPONG_0,
		@@ -817,7 +817,7 @@ static int sde_encoder_phys_wb_atomic_check(
		}

		static void _sde_encoder_phys_wb_update_cwb_flush(
		struct sde_encoder_phys *phys_enc)
		struct sde_encoder_phys *phys_enc, bool enable)
		{
		struct sde_encoder_phys_wb *wb_enc;
		struct sde_hw_wb *hw_wb;
		@@ -879,7 +879,7 @@ static void _sde_encoder_phys_wb_update_cwb_flush(

		if (hw_wb->ops.program_cwb_ctrl)
		hw_wb->ops.program_cwb_ctrl(hw_wb, cwb_idx,
		src_pp_idx, dspp_out);
		src_pp_idx, dspp_out, enable);

		if (hw_ctl->ops.update_bitmask_cwb)
		hw_ctl->ops.update_bitmask_cwb(hw_ctl,
		@@ -1324,7 +1324,7 @@ static int sde_encoder_phys_wb_prepare_for_kickoff(

		_sde_encoder_phys_wb_update_flush(phys_enc);

		_sde_encoder_phys_wb_update_cwb_flush(phys_enc);
		_sde_encoder_phys_wb_update_cwb_flush(phys_enc, true);

		/* vote for iommu/clk/bus */
		wb_enc->start_time = ktime_get();
		@@ -1562,6 +1562,7 @@ static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
		/* avoid reset frame for CWB */
		if (phys_enc->in_clone_mode) {
		_sde_encoder_phys_wb_setup_cwb(phys_enc, false);
		_sde_encoder_phys_wb_update_cwb_flush(phys_enc, false);
		phys_enc->in_clone_mode = false;
		goto exit;
		}

msm/sde/sde_hw_ctl.c

+26 −20

Original line number	Diff line number	Diff line
		@@ -1012,12 +1012,8 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
		struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx)
		{
		struct sde_hw_blk_reg_map *c;
		u32 intf_active = 0;
		u32 intf_flush = 0;
		u32 merge_3d_active = 0;
		u32 merge_3d_flush = 0;
		u32 wb_active = 0;
		u32 wb_flush = 0;
		u32 intf_active = 0, wb_active = 0, merge_3d_active = 0;
		u32 intf_flush = 0, wb_flush = 0;
		u32 i;

		if (!ctx \|\| !cfg) {
		@@ -1042,25 +1038,30 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,

		if (merge_3d_idx) {
		/* disable and flush merge3d_blk */
		merge_3d_flush = BIT(merge_3d_idx - MERGE_3D_0);
		ctx->flush.pending_merge_3d_flush_mask =
		BIT(merge_3d_idx - MERGE_3D_0);
		merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
		ctx->flush.pending_merge_3d_flush_mask = merge_3d_flush;
		SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
		}

		sde_hw_ctl_clear_all_blendstages(ctx);

		if (cfg->intf_count) {
		ctx->flush.pending_intf_flush_mask = intf_flush;
		ctx->flush.pending_wb_flush_mask = wb_flush;


		UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
		SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
		SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
		}

		if (cfg->wb_count) {
		ctx->flush.pending_wb_flush_mask = wb_flush;
		UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
		SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
		}
		return 0;
		}

		static int sde_hw_ctl_update_cwb_cfg(struct sde_hw_ctl *ctx,
		struct sde_hw_intf_cfg_v1 *cfg)
		struct sde_hw_intf_cfg_v1 *cfg, bool enable)
		{
		int i;
		u32 cwb_active = 0;
		@@ -1084,11 +1085,16 @@ static int sde_hw_ctl_update_cwb_cfg(struct sde_hw_ctl *ctx,
		merge_3d_active \|= BIT(cfg->merge_3d[i] - MERGE_3D_0);
		}

		if (enable) {
		wb_active = BIT(2);
		SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
		SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
		SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);

		} else {
		SDE_REG_WRITE(c, CTL_WB_ACTIVE, 0x0);
		SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, 0x0);
		SDE_REG_WRITE(c, CTL_CWB_ACTIVE, 0x0);
		}
		return 0;
		}

msm/sde/sde_hw_ctl.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -249,10 +249,11 @@ struct sde_hw_ctl_ops {
		/** update cwb for ctl_path
		* @ctx : ctl path ctx pointer
		* @cfg : interface config structure pointer
		* @enable : enable/disable the cwb hw block
		* @Return: error code
		*/
		int (update_cwb_cfg)(struct sde_hw_ctl ctx,
		struct sde_hw_intf_cfg_v1 *cfg);
		struct sde_hw_intf_cfg_v1 *cfg, bool enable);

		/**
		* Setup ctl_path interface config for SDE_CTL_ACTIVE_CFG

msm/sde/sde_hw_intf.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -368,13 +368,13 @@ static void sde_hw_intf_bind_pingpong_blk(
		mux_cfg = SDE_REG_READ(c, INTF_MUX);
		mux_cfg &= ~0xf;

		if (enable)
		if (enable) {
		mux_cfg \|= (pp - PINGPONG_0) & 0x7;
		else
		mux_cfg \|= 0xf;

		if (intf->cfg.split_link_en)
		mux_cfg = 0x60000;
		} else {
		mux_cfg = 0xf000f;
		}

		SDE_REG_WRITE(c, INTF_MUX, mux_cfg);
		}