Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 35717d8d authored by John Ogness's avatar John Ogness Committed by David S. Miller
Browse files

drivers: net: cpsw: Fix TX_IN_SEL offset 



The TX_IN_SEL offset for the CPSW_PORT/TX_IN_CTL register was
incorrect. This caused the Dual MAC mode to never get set when
it should. It also caused possible unintentional setting of a
bit in the CPSW_PORT/TX_BLKS_REM register.

The purpose of setting the Dual MAC mode for this register is to:

    "... allow packets from both ethernet ports to be written into
     the FIFO without one port starving the other port."
					- AM335x ARM TRM

Signed-off-by: default avatarJohn Ogness <john.ogness@linutronix.de>
Reviewed-by: default avatarMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9f458945

drivers/net/ethernet/ti/cpsw.c

+3 −3
Original line number Diff line number Diff line
@@ -129,9 +129,9 @@ do { \ 
#define CPSW_VLAN_AWARE		BIT(1)

#define CPSW_ALE_VLAN_AWARE	1



#define CPSW_FIFO_NORMAL_MODE		(0 << 15)

#define CPSW_FIFO_DUAL_MAC_MODE		(1 << 15)

#define CPSW_FIFO_RATE_LIMIT_MODE	(2 << 15)

#define CPSW_FIFO_NORMAL_MODE		(0 << 16)

#define CPSW_FIFO_DUAL_MAC_MODE		(1 << 16)

#define CPSW_FIFO_RATE_LIMIT_MODE	(2 << 16)



#define CPSW_INTPACEEN		(0x3f << 16)

#define CPSW_INTPRESCALE_MASK	(0x7FF << 0)