Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +3 −1 Original line number Diff line number Diff line Loading @@ -5136,7 +5136,9 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( list_for_each_entry(isp_ife_camif_res, &ife_hwr_mgr_ctx->res_list_ife_src, list) { if (isp_ife_camif_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) if ((isp_ife_camif_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) || (isp_ife_camif_res->res_id != CAM_ISP_HW_VFE_IN_CAMIF)) continue; hw_res_left = isp_ife_camif_res->hw_res[0]; Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +4 −0 Original line number Diff line number Diff line Loading @@ -652,6 +652,10 @@ int cam_vfe_start(void *hw_priv, void *start_args, uint32_t arg_size) if (isp_res->irq_handle < 1) rc = -ENOMEM; } else if (isp_res->rdi_only_ctx) { if (strnstr(soc_info->compatible, "lite", strlen(soc_info->compatible)) != NULL) rdi_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = 0x3333; isp_res->irq_handle = cam_irq_controller_subscribe_irq( core_info->vfe_irq_controller, Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c +4 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,10 @@ static int cam_vfe_get_dt_properties(struct cam_hw_soc_info *soc_info) return rc; } if (strnstr(soc_info->compatible, "lite", strlen(soc_info->compatible)) != NULL) goto end; switch (soc_info->hw_version) { case CAM_CPAS_TITAN_480_V100: num_ubwc_cfg = of_property_count_u32_elems(of_node, Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h +3 −3 Original line number Diff line number Diff line Loading @@ -152,7 +152,7 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x2, .epoch_line_cfg = 0x00140014, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x10, .epoch0_irq_mask = 0x40, .epoch1_irq_mask = 0x80, Loading @@ -164,7 +164,7 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x4, .epoch_line_cfg = 0x00140014, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x100, .epoch0_irq_mask = 0x400, .epoch1_irq_mask = 0x800, Loading @@ -176,7 +176,7 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x8, .epoch_line_cfg = 0x00140014, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x1000, .epoch0_irq_mask = 0x4000, .epoch1_irq_mask = 0x8000, Loading drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite48x.h +8 −8 Original line number Diff line number Diff line Loading @@ -107,8 +107,8 @@ static struct cam_vfe_camif_lite_ver3_reg vfe48x_camif_rdi[4] = { static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x11, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x1, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x1, .epoch0_irq_mask = 0x4, .epoch1_irq_mask = 0x8, Loading @@ -119,8 +119,8 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { }, { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x22, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x2, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x10, .epoch0_irq_mask = 0x40, .epoch1_irq_mask = 0x80, Loading @@ -131,8 +131,8 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { }, { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x44, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x4, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x100, .epoch0_irq_mask = 0x400, .epoch1_irq_mask = 0x800, Loading @@ -143,8 +143,8 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { }, { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x88, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x8, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x1000, .epoch0_irq_mask = 0x4000, .epoch1_irq_mask = 0x8000, Loading Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +3 −1 Original line number Diff line number Diff line Loading @@ -5136,7 +5136,9 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( list_for_each_entry(isp_ife_camif_res, &ife_hwr_mgr_ctx->res_list_ife_src, list) { if (isp_ife_camif_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) if ((isp_ife_camif_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) || (isp_ife_camif_res->res_id != CAM_ISP_HW_VFE_IN_CAMIF)) continue; hw_res_left = isp_ife_camif_res->hw_res[0]; Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +4 −0 Original line number Diff line number Diff line Loading @@ -652,6 +652,10 @@ int cam_vfe_start(void *hw_priv, void *start_args, uint32_t arg_size) if (isp_res->irq_handle < 1) rc = -ENOMEM; } else if (isp_res->rdi_only_ctx) { if (strnstr(soc_info->compatible, "lite", strlen(soc_info->compatible)) != NULL) rdi_irq_reg_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = 0x3333; isp_res->irq_handle = cam_irq_controller_subscribe_irq( core_info->vfe_irq_controller, Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c +4 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,10 @@ static int cam_vfe_get_dt_properties(struct cam_hw_soc_info *soc_info) return rc; } if (strnstr(soc_info->compatible, "lite", strlen(soc_info->compatible)) != NULL) goto end; switch (soc_info->hw_version) { case CAM_CPAS_TITAN_480_V100: num_ubwc_cfg = of_property_count_u32_elems(of_node, Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h +3 −3 Original line number Diff line number Diff line Loading @@ -152,7 +152,7 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x2, .epoch_line_cfg = 0x00140014, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x10, .epoch0_irq_mask = 0x40, .epoch1_irq_mask = 0x80, Loading @@ -164,7 +164,7 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x4, .epoch_line_cfg = 0x00140014, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x100, .epoch0_irq_mask = 0x400, .epoch1_irq_mask = 0x800, Loading @@ -176,7 +176,7 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_rdi_reg_data[3] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x8, .epoch_line_cfg = 0x00140014, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x1000, .epoch0_irq_mask = 0x4000, .epoch1_irq_mask = 0x8000, Loading
drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite48x.h +8 −8 Original line number Diff line number Diff line Loading @@ -107,8 +107,8 @@ static struct cam_vfe_camif_lite_ver3_reg vfe48x_camif_rdi[4] = { static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x11, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x1, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x1, .epoch0_irq_mask = 0x4, .epoch1_irq_mask = 0x8, Loading @@ -119,8 +119,8 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { }, { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x22, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x2, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x10, .epoch0_irq_mask = 0x40, .epoch1_irq_mask = 0x80, Loading @@ -131,8 +131,8 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { }, { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x44, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x4, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x100, .epoch0_irq_mask = 0x400, .epoch1_irq_mask = 0x800, Loading @@ -143,8 +143,8 @@ static struct cam_vfe_camif_lite_ver3_reg_data vfe48x_camif_rdi_reg_data[4] = { }, { .extern_reg_update_shift = 0, .reg_update_cmd_data = 0x88, .epoch_line_cfg = 0x00140014, .reg_update_cmd_data = 0x8, .epoch_line_cfg = 0x0, .sof_irq_mask = 0x1000, .epoch0_irq_mask = 0x4000, .epoch1_irq_mask = 0x8000, Loading