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Commit 341c5baf authored by Sunil Paidimarri's avatar Sunil Paidimarri Committed by Lakshit Tyagi
Browse files

data-kernel: EMAC: boot up KPI changes 



Read early ethernet dtsi flag to enable this feature.
Disable autoneg and configure MAC and PHY with 100 Mbps
link speed.
Read MAC addr, IPv4 and IPv6 addresses from kernel cmd
line parameters in order to assign these to ethernet
interface

Change-Id: I1e42e116afa818dd0afad89caed65ce7b2c274cb
CRs-Fixed: 2333667
Acked-by: default avatarLakshit Tyagi <ltyagi@codeaurora.org>
Acked-by: default avatarNisha Menon <nmenon@qti.qualcomm.com>
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent 5debe039

drivers/emac-dwc-eqos/DWC_ETH_QOS_dev.c

+6 −2
Original line number Diff line number Diff line
@@ -4795,8 +4795,6 @@ static INT DWC_ETH_QOS_yinit(struct DWC_ETH_QOS_prv_data *pdata) 
	for (QINX = 0; QINX < DWC_ETH_QOS_TX_QUEUE_CNT; QINX++)

		configure_mtl_queue(QINX, pdata);



	/* Mapping MTL Rx queue and DMA Rx channel. */

	MTL_RQDCM0R_RGWR(0x3020100);

#ifdef DWC_ETH_QOS_CERTIFICATION_PKTBURSTCNT

	/* enable tx drop status */

	MTL_OMR_DTXSTS_UDFWR(0x1);
@@ -4805,6 +4803,12 @@ static INT DWC_ETH_QOS_yinit(struct DWC_ETH_QOS_prv_data *pdata) 
	configure_mac(pdata);

	configure_dma_sys_bus(pdata);



	/* Mapping MTL Rx queue and DMA Rx channel. */

	if (pdata->res_data->early_eth_en)

		MTL_RQDCM0R_RGWR(0x3020101);

	else /* Mapped RX queue 0 to DMA channel 1 */

		MTL_RQDCM0R_RGWR(0x3020100);



	for (QINX = 0; QINX < DWC_ETH_QOS_TX_QUEUE_CNT; QINX++) {

		if (pdata->ipa_enabled && QINX == IPA_DMA_TX_CH)

			continue;

drivers/emac-dwc-eqos/DWC_ETH_QOS_drv.c

+44 −11
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ extern wait_queue_head_t avb_class_b_msg_wq; 
#define DEFAULT_START_TIME 0x1900



static INT DWC_ETH_QOS_GSTATUS;

extern struct ip_params pparams;



/* SA(Source Address) operations on TX */

unsigned char mac_addr0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 };
@@ -1830,6 +1831,37 @@ static void DWC_ETH_QOS_default_rx_confs(struct DWC_ETH_QOS_prv_data *pdata) 
	DBGPR("<--DWC_ETH_QOS_default_rx_confs\n");

}



int DWC_ETH_QOS_add_ipv6addr(struct ip_params *ip_info, struct net_device *dev)

{

	int res=0;

	struct in6_ifreq ir6;

	char* prefix;



	/*For valid IPv6 address*/



	memset(&ir6, 0, sizeof(ir6));

	if (1 == in6_pton(ip_info->ipv6_addr, -1, (u8*)&ir6.ifr6_addr.s6_addr32, -1, NULL)) {

		EMACDBG( "Setup IPv6 address!\r\n");

		ir6.ifr6_ifindex = dev->ifindex;

		//ir6.ifr6_prefixlen = 0;

		if ((prefix = strchr(ip_info->ipv6_addr, '/')) == NULL)

			ir6.ifr6_prefixlen = 0;

		else {

			ir6.ifr6_prefixlen = simple_strtoul(prefix+1, NULL, 0);

			if (ir6.ifr6_prefixlen > 128)

				ir6.ifr6_prefixlen = 0;

		}

		res = addrconf_add_ifaddr(&init_net, (struct in6_ifreq __user *) &ir6);

		if (res)

			EMACERR( "Can't setup IPv6 address!\r\n");

		else

			EMACDBG("Assigned IPv6 address: %s\r\n", ip_info->ipv6_addr);



	}



	return res;

}



/*!

 * \brief API to open a device for data transmission & reception.

 *
@@ -1934,6 +1966,9 @@ static int DWC_ETH_QOS_open(struct net_device *dev) 
	netif_tx_disable(dev);

#endif /* end of DWC_ETH_QOS_CONFIG_PGTEST */



	//if (pdata->res_data->early_eth_en)

		//DWC_ETH_QOS_add_ipv6addr(&pparams, dev);



	EMACDBG("<--DWC_ETH_QOS_open\n");



	return ret;
@@ -5083,7 +5118,7 @@ static int ETH_PTPCLK_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data 
	}



	if (eth_pps_cfg->ptpclk_freq > DWC_ETH_QOS_SYSCLOCK){

		EMACINFO("PPS: PTPCLK_Config: freq=%dHz is too high. Cannot config it\n",

		EMACDBG("PPS: PTPCLK_Config: freq=%dHz is too high. Cannot config it\n",

			eth_pps_cfg->ptpclk_freq );

		return -1;

	}
@@ -5093,7 +5128,7 @@ static int ETH_PTPCLK_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data 
	val += (DWC_ETH_QOS_SYSCLOCK/2);

	val = div_u64(val, DWC_ETH_QOS_SYSCLOCK);

	if ( val > 0xFFFFFFFF) val = 0xFFFFFFFF;

	EMACINFO("PPS: PTPCLK_Config: freq=%dHz, addend_reg=0x%x\n",

	EMACDBG("PPS: PTPCLK_Config: freq=%dHz, addend_reg=0x%x\n",

				eth_pps_cfg->ptpclk_freq, (unsigned int)val);



	pdata->default_addend = val;
@@ -5283,13 +5318,13 @@ int ETH_PPSOUT_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data_struct 
	if (width >= interval) width = interval - 1;

	if (width < 0) width = 0;



	EMACINFO("PPS: PPSOut_Config: freq=%dHz, ch=%d, duty=%d\n",

	EMACDBG("PPS: PPSOut_Config: freq=%dHz, ch=%d, duty=%d\n",

				eth_pps_cfg->ppsout_freq,

				eth_pps_cfg->ppsout_ch,

				eth_pps_cfg->ppsout_duty);

	EMACINFO(" PPS: with PTP Clock freq=%dHz\n", pdata->ptpclk_freq);

	EMACDBG(" PPS: with PTP Clock freq=%dHz\n", pdata->ptpclk_freq);



	EMACINFO("PPS: PPSOut_Config: interval=%d, width=%d\n", interval, width);

	EMACDBG("PPS: PPSOut_Config: interval=%d, width=%d\n", interval, width);



	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1) {

		//calculate interval & width
@@ -5372,7 +5407,7 @@ int ETH_PPSOUT_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data_struct 
		}

		break;

	default:

		EMACINFO("PPS: PPS output channel is invalid (only CH0/CH1/CH2/CH3 is supported).\n");

		EMACDBG("PPS: PPS output channel is invalid (only CH0/CH1/CH2/CH3 is supported).\n");

		return -EOPNOTSUPP;

	}
@@ -6059,7 +6094,6 @@ static int DWC_ETH_QOS_handle_hwtstamp_ioctl(struct DWC_ETH_QOS_prv_data *pdata, 
		temp = (u64)(50000000ULL << 32);

		pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK);

		EMACINFO("Using default PTP clock = 250MHz\n");

	}

#else

		temp = (u64)(50000000ULL << 32);

		pdata->default_addend = div_u64(temp, DWC_ETH_QOS_SYSCLOCK);
@@ -6220,7 +6254,7 @@ static int DWC_ETH_QOS_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 
	case DWC_ETH_QOS_PRV_IOCTL_IPA:

		if (!pdata->prv_ipa.ipa_uc_ready ) {

			ret = -EAGAIN;

			EMACINFO("IPA or IPA uc is not ready \n");

			EMACDBG("IPA or IPA uc is not ready \n");

			break;

		}

		ret = DWC_ETH_QOS_handle_prv_ioctl_ipa(pdata, ifr);
@@ -6459,8 +6493,7 @@ static int DWC_ETH_QOS_vlan_rx_add_vid( 
	int crc32_val = 0;

	unsigned int enb_12bit_vhash;



	dev_alert(&pdata->pdev->dev, "-->DWC_ETH_QOS_vlan_rx_add_vid: vid = %d\n",

		  vid);

	EMACDBG("-->DWC_ETH_QOS_vlan_rx_add_vid: vid = %d\n", vid);



	if (pdata->vlan_hash_filtering) {

		/* The upper 4 bits of the calculated CRC are used to
@@ -6493,7 +6526,7 @@ static int DWC_ETH_QOS_vlan_rx_add_vid( 
		pdata->vlan_ht_or_id = vid;

	}



	dev_alert(&pdata->pdev->dev, "<--DWC_ETH_QOS_vlan_rx_add_vid\n");

	EMACDBG("<--DWC_ETH_QOS_vlan_rx_add_vid\n");

	return 0;

}

drivers/emac-dwc-eqos/DWC_ETH_QOS_ethtool.c

+2 −2
Original line number Diff line number Diff line
@@ -1084,7 +1084,7 @@ static void DWC_ETH_QOS_get_ethtool_stats( 
	

	/* Update IPA stats */

	if (pdata->ipa_enabled) {

		EMACINFO("Add IPA stats\n");

		EMACDBG("Add IPA stats\n");

		DWC_ETH_QOS_ipa_stats_read(pdata);

		for (i = 0; i < DWC_ETH_QOS_IPA_STAT_LEN; i++) {

			char *p = (char *)pdata +
@@ -1203,7 +1203,7 @@ static int DWC_ETH_QOS_get_ts_info(struct net_device *dev, 
	struct DWC_ETH_QOS_prv_data *pdata = netdev_priv(dev);

	DBGPR("-->DWC_ETH_QOS_get_ts_info\n");

	info->phc_index = DWC_ETH_QOS_phc_index(pdata);

	EMACINFO("PHC index = %d\n", info->phc_index);

	EMACDBG("PHC index = %d\n", info->phc_index);

	DBGPR("<--DWC_ETH_QOS_get_ts_info\n");

	return 0;

}

drivers/emac-dwc-eqos/DWC_ETH_QOS_ipa.c

+25 −22
Original line number Diff line number Diff line
@@ -104,7 +104,7 @@ void DWC_ETH_QOS_ipa_offload_event_handler( 


	IPA_LOCK();



	EMACINFO("Enter: event=%s\n", IPA_OFFLOAD_EVENT_string[ev]);

	EMACDBG("Enter: event=%s\n", IPA_OFFLOAD_EVENT_string[ev]);

	EMACDBG("PHY_link=%d\n"

	"emac_dev_ready=%d\n"

	"ipa_ready=%d\n"
@@ -202,7 +202,7 @@ void DWC_ETH_QOS_ipa_offload_event_handler( 
	case EV_IPA_UC_READY:

		{

			pdata->prv_ipa.ipa_uc_ready = true;

			EMACINFO("%s:%d ipa uC is ready\n", __func__, __LINE__);

			EMACDBG("%s:%d ipa uC is ready\n", __func__, __LINE__);



			if (!pdata->prv_ipa.emac_dev_ready)

				break;
@@ -265,7 +265,7 @@ void DWC_ETH_QOS_ipa_offload_event_handler( 
		break;

	}



	EMACINFO("Exit: event=%s\n", IPA_OFFLOAD_EVENT_string[ev]);

	EMACDBG("Exit: event=%s\n", IPA_OFFLOAD_EVENT_string[ev]);

	IPA_UNLOCK();

}
@@ -281,7 +281,7 @@ int DWC_ETH_QOS_enable_ipa_offload(struct DWC_ETH_QOS_prv_data *pdata) 
			EMACERR("IPA Offload Init Failed \n");

			goto fail;

		}

		EMACINFO("IPA Offload Initialized Successfully \n");

		EMACDBG("IPA Offload Initialized Successfully \n");

		pdata->prv_ipa.ipa_offload_init = true;

	}
@@ -292,7 +292,7 @@ int DWC_ETH_QOS_enable_ipa_offload(struct DWC_ETH_QOS_prv_data *pdata) 
			pdata->prv_ipa.ipa_offload_conn = false;

			goto fail;

		}

		EMACINFO("IPA Offload Connect Successfully\n");

		EMACDBG("IPA Offload Connect Successfully\n");

		pdata->prv_ipa.ipa_offload_conn = true;



		/*Initialize DMA CHs for offload*/
@@ -305,12 +305,12 @@ int DWC_ETH_QOS_enable_ipa_offload(struct DWC_ETH_QOS_prv_data *pdata) 


	if (!pdata->prv_ipa.ipa_debugfs_exists) {

		if (!DWC_ETH_QOS_ipa_create_debugfs(pdata)) {

			EMACINFO("eMAC Debugfs created  \n");

			EMACDBG("eMAC Debugfs created  \n");

			pdata->prv_ipa.ipa_debugfs_exists = true;

		} else EMACERR("eMAC Debugfs failed \n");

	}



	EMACINFO("IPA Offload Enabled successfully\n");

	EMACDBG("IPA Offload Enabled successfully\n");

	return ret;



fail:
@@ -318,7 +318,7 @@ int DWC_ETH_QOS_enable_ipa_offload(struct DWC_ETH_QOS_prv_data *pdata) 
		if( DWC_ETH_QOS_ipa_offload_disconnect(pdata) )

			EMACERR("IPA Offload Disconnect Failed \n");

		else

			EMACINFO("IPA Offload Disconnect Successfully \n");

			EMACDBG("IPA Offload Disconnect Successfully \n");

		pdata->prv_ipa.ipa_offload_conn = false;

	}
@@ -326,7 +326,7 @@ int DWC_ETH_QOS_enable_ipa_offload(struct DWC_ETH_QOS_prv_data *pdata) 
		if ( DWC_ETH_QOS_ipa_offload_cleanup(pdata ))

			EMACERR("IPA Offload Cleanup Failed \n");

		else

			EMACINFO("IPA Offload Cleanup Success \n");

			EMACDBG("IPA Offload Cleanup Success \n");

		pdata->prv_ipa.ipa_offload_init = false;

	}
@@ -355,7 +355,7 @@ int DWC_ETH_QOS_disable_ipa_offload(struct DWC_ETH_QOS_prv_data *pdata) 
			EMACERR("IPA Offload Cleanup Failed, err: %d\n", ret);

			return ret;

		}

		EMACINFO("IPA Offload Cleanup Success \n");

		EMACDBG("IPA Offload Cleanup Success \n");

		pdata->prv_ipa.ipa_offload_init = false;

	}
@@ -534,12 +534,12 @@ static int DWC_ETH_QOS_ipa_ready(struct DWC_ETH_QOS_prv_data *pdata) 
		ret = ipa_register_ipa_ready_cb(DWC_ETH_QOS_ipa_ready_cb,

										(void *)pdata);

		if (ret == -ENXIO) {

			EMACINFO("%s: IPA driver context is not even ready\n", __func__);

			EMACDBG("%s: IPA driver context is not even ready\n", __func__);

			return ret;

		}



		if (ret != -EEXIST) {

			EMACINFO("%s:%d register ipa ready cb\n", __func__, __LINE__);

			EMACDBG("%s:%d register ipa ready cb\n", __func__, __LINE__);

			return ret;

		}

	}
@@ -566,7 +566,7 @@ static int DWC_ETH_QOS_ipa_uc_ready(struct DWC_ETH_QOS_prv_data *pdata) 


	ret = ipa_uc_offload_reg_rdyCB(&param);

	if (ret == 0 && param.is_uC_ready) {

		EMACINFO("%s:%d ipa uc ready\n", __func__, __LINE__);

		EMACDBG("%s:%d ipa uc ready\n", __func__, __LINE__);

		pdata->prv_ipa.ipa_uc_ready = true;

	}
@@ -748,7 +748,7 @@ static int DWC_ETH_QOS_ipa_offload_init(struct DWC_ETH_QOS_prv_data *pdata) 
		ipa_vlan_mode = 0;

	}



	EMACINFO("IPA VLAN mode %d\n", ipa_vlan_mode);

	EMACDBG("IPA VLAN mode %d\n", ipa_vlan_mode);



	memset(&in, 0, sizeof(in));

	memset(&out, 0, sizeof(out));
@@ -817,7 +817,7 @@ int DWC_ETH_QOS_ipa_offload_cleanup(struct DWC_ETH_QOS_prv_data *pdata) 
	struct DWC_ETH_QOS_prv_ipa_data *ntn_ipa = &pdata->prv_ipa;

	int ret = 0;



	EMACINFO("%s - begin\n", __func__);

	EMACDBG("%s - begin\n", __func__);



	if (!pdata) {

		EMACERR("Null Param %s \n", __func__);
@@ -836,7 +836,7 @@ int DWC_ETH_QOS_ipa_offload_cleanup(struct DWC_ETH_QOS_prv_data *pdata) 
		return -1;

	}



	EMACINFO("%s - end\n", __func__);

	EMACDBG("%s - end\n", __func__);



	return 0;

}
@@ -969,7 +969,7 @@ static int DWC_ETH_QOS_ipa_offload_connect(struct DWC_ETH_QOS_prv_data *pdata) 
	int i = 0;





	EMACINFO("%s - begin\n", __func__);

	EMACDBG("%s - begin\n", __func__);



	if(!pdata) {

		EMACERR( "Null Param %s \n", __func__);
@@ -1070,9 +1070,9 @@ static int DWC_ETH_QOS_ipa_offload_connect(struct DWC_ETH_QOS_prv_data *pdata) 
	}



	/* Dump UL and DL Setups */

	EMACINFO("IPA Offload UL client %d ring_base_pa 0x%x ntn_ring_size %d buff_pool_base_pa 0x%x num_buffers %d data_buff_size %d ntn_reg_base_ptr_pa 0x%x\n",

	EMACDBG("IPA Offload UL client %d ring_base_pa 0x%x ntn_ring_size %d buff_pool_base_pa 0x%x num_buffers %d data_buff_size %d ntn_reg_base_ptr_pa 0x%x\n",

		rx_setup_info.client, rx_setup_info.ring_base_pa, rx_setup_info.ntn_ring_size, rx_setup_info.buff_pool_base_pa, rx_setup_info.num_buffers, rx_setup_info.data_buff_size, rx_setup_info.ntn_reg_base_ptr_pa);

	EMACINFO("IPA Offload DL client %d ring_base_pa 0x%x ntn_ring_size %d buff_pool_base_pa 0x%x num_buffers %d data_buff_size %d ntn_reg_base_ptr_pa 0x%x\n",

	EMACDBG("IPA Offload DL client %d ring_base_pa 0x%x ntn_ring_size %d buff_pool_base_pa 0x%x num_buffers %d data_buff_size %d ntn_reg_base_ptr_pa 0x%x\n",

		tx_setup_info.client, tx_setup_info.ring_base_pa, tx_setup_info.ntn_ring_size, tx_setup_info.buff_pool_base_pa, tx_setup_info.num_buffers, tx_setup_info.data_buff_size, tx_setup_info.ntn_reg_base_ptr_pa);



	in.u.ntn.ul = rx_setup_info;
@@ -1085,6 +1085,9 @@ static int DWC_ETH_QOS_ipa_offload_connect(struct DWC_ETH_QOS_prv_data *pdata) 
		goto mem_free;

	}



    /* Mapped RX queue 0 to DMA channel 0 on successful IPA offload connect */

    MTL_RQDCM0R_RGWR(0x3020100);



    ntn_ipa->uc_db_rx_addr = out.u.ntn.ul_uc_db_pa;

    ntn_ipa->uc_db_tx_addr = out.u.ntn.dl_uc_db_pa;
@@ -1140,7 +1143,7 @@ static int DWC_ETH_QOS_ipa_offload_connect(struct DWC_ETH_QOS_prv_data *pdata) 
		}

	}



	EMACINFO("%s - end \n", __func__);

	EMACDBG("%s - end \n", __func__);

	return 0;

}
@@ -1160,7 +1163,7 @@ static int DWC_ETH_QOS_ipa_offload_disconnect(struct DWC_ETH_QOS_prv_data *pdata 
	struct DWC_ETH_QOS_prv_ipa_data *ntn_ipa = &pdata->prv_ipa;

	int ret = 0;



	EMACINFO("%s - begin \n", __func__);

	EMACDBG("%s - begin \n", __func__);



	if(!pdata) {

		EMACERR( "Null Param %s \n", __func__);
@@ -1173,7 +1176,7 @@ static int DWC_ETH_QOS_ipa_offload_disconnect(struct DWC_ETH_QOS_prv_data *pdata 
		return ret;

	}



	EMACINFO("%s - end \n", __func__);

	EMACDBG("%s - end \n", __func__);

	return 0;

}

drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c

+48 −15
Original line number Diff line number Diff line
@@ -295,6 +295,9 @@ static INT DWC_ETH_QOS_mdio_reset(struct mii_bus *bus) 


	DBGPR_MDIO("-->DWC_ETH_QOS_mdio_reset: phyaddr : %d\n", pdata->phyaddr);



	if (pdata->res_data->early_eth_en)

		return 0;



#if 0 /* def DWC_ETH_QOS_CONFIG_PGTEST */

	pr_alert("PHY Programming for Autoneg disable\n");

	hw_if->read_phy_regs(pdata->phyaddr, MII_BMCR, &phydata);
@@ -458,7 +461,7 @@ static void DWC_ETH_QOS_set_phy_hibernation_mode(struct DWC_ETH_QOS_prv_data *pd 
								uint mode)

{

	u32 phydata = 0;

	EMACINFO("Enter\n");

	EMACDBG("Enter\n");



	DWC_ETH_QOS_mdio_write_direct(pdata, pdata->phyaddr,

				DWC_ETH_QOS_PHY_DEBUG_PORT_ADDR_OFFSET,
@@ -467,7 +470,7 @@ static void DWC_ETH_QOS_set_phy_hibernation_mode(struct DWC_ETH_QOS_prv_data *pd 
				DWC_ETH_QOS_PHY_DEBUG_PORT_DATAPORT,

				&phydata);



	EMACINFO("value read 0x%x\n", phydata);

	EMACDBG("value read 0x%x\n", phydata);



	phydata = ((phydata & DWC_ETH_QOS_PHY_HIB_CTRL_PS_HIB_EN_WR_MASK)

			   | ((DWC_ETH_QOS_PHY_HIB_CTRL_PS_HIB_EN_MASK & mode) << 15));
@@ -482,7 +485,7 @@ static void DWC_ETH_QOS_set_phy_hibernation_mode(struct DWC_ETH_QOS_prv_data *pd 
				DWC_ETH_QOS_PHY_DEBUG_PORT_DATAPORT,

				&phydata);



	EMACINFO("Exit value written 0x%x\n", phydata);

	EMACDBG("Exit value written 0x%x\n", phydata);

}



/*!
@@ -897,6 +900,11 @@ void DWC_ETH_QOS_adjust_link(struct net_device *dev) 
	if (!phydev)

		return;



	if (pdata->oldlink == -1 && !phydev->link) {

		pdata->oldlink = phydev->link;

		return;

	}



	DBGPR_MDIO(

		"-->DWC_ETH_QOS_adjust_link. address %d link %d\n",

		phydev->mdio.addr, phydev->link);
@@ -1038,7 +1046,7 @@ static void DWC_ETH_QOS_request_phy_wol(struct DWC_ETH_QOS_prv_data *pdata) 
				enable_irq_wake(pdata->phy_irq);



				device_set_wakeup_enable(&pdata->pdev->dev, 1);

				EMACINFO("Enabled WoL[0x%x] in %s\n", wol.wolopts,

				EMACDBG("Enabled WoL[0x%x] in %s\n", wol.wolopts,

						 pdata->phydev->drv->name);

			}

		}
@@ -1113,19 +1121,32 @@ static int DWC_ETH_QOS_init_phy(struct net_device *dev) 
		EMACDBG("Phy polling enabled\n");

#endif



	if (pdata->interface == PHY_INTERFACE_MODE_GMII ||

	    pdata->interface == PHY_INTERFACE_MODE_RGMII) {





	if (pdata->res_data->early_eth_en ) {

		phydev->autoneg = AUTONEG_DISABLE;

		phydev->speed = SPEED_100;

		phy_set_max_speed(phydev, SPEED_100);

		phydev->duplex = DUPLEX_FULL;

		phydev->supported = SUPPORTED_100baseT_Full | SUPPORTED_TP | SUPPORTED_MII;

		phydev->supported &= ~(SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half | SUPPORTED_1000baseT_Half);

		phydev->supported &= ~SUPPORTED_Autoneg;

		phydev->advertising = phydev->supported;

		phydev->advertising &= ~ADVERTISED_Autoneg;

		EMACDBG("Set max speed to SPEED_100 as early ethernet enabled\n");

	}

	else {

		if (pdata->interface == PHY_INTERFACE_MODE_GMII || pdata->interface == PHY_INTERFACE_MODE_RGMII) {

			phy_set_max_speed(phydev, SPEED_1000);

			/* Half duplex not supported */

			phydev->supported &= ~(SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half | SUPPORTED_1000baseT_Half);

	} else if ((pdata->interface == PHY_INTERFACE_MODE_MII) ||

		   (pdata->interface == PHY_INTERFACE_MODE_RMII)) {

		} else if ((pdata->interface == PHY_INTERFACE_MODE_MII) || (pdata->interface == PHY_INTERFACE_MODE_RMII)) {

			phy_set_max_speed(phydev, SPEED_100);

			/* Half duplex is not supported */

			phydev->supported &= ~(SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half);

		}



		phydev->advertising = phydev->supported;

	}



	pdata->phydev = phydev;
@@ -1218,6 +1239,7 @@ int DWC_ETH_QOS_mdio_register(struct net_device *dev) 
	int ret = Y_SUCCESS;

	int phy_reg_read_status, mii_status;

	u32 phy_id, phy_id1, phy_id2;

	u32 phydata = 0;



	DBGPR_MDIO("-->DWC_ETH_QOS_mdio_register\n");
@@ -1252,6 +1274,17 @@ int DWC_ETH_QOS_mdio_register(struct net_device *dev) 
	pdata->phy_intr_en = false;

	pdata->always_on_phy = false;



	if(pdata->res_data->early_eth_en) {

		EMACDBG("Updated speed to 100 in emac\n");

		pdata->hw_if.set_mii_speed_100();



		phydata = BMCR_SPEED100;

		phydata |= BMCR_FULLDPLX;

		EMACDBG("Updated speed to 100 and autoneg disable\n");

		pdata->hw_if.write_phy_regs(pdata->phyaddr,

				MII_BMCR, phydata);

	}



	DBGPHY_REGS(pdata);



	new_bus = mdiobus_alloc();