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Commit 337cd564 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "include: dt-bindings: clock: Add clock IDs supported on Lagoon"

parents 368c5bbf a4d74466

include/dt-bindings/clock/qcom,camcc-lagoon.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_LAGOON_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_LAGOON_H



/* CAM_CC clocks */

#define CAM_CC_PLL0			0

#define CAM_CC_PLL0_OUT_EVEN		1

#define CAM_CC_PLL1			2

#define CAM_CC_PLL1_OUT_EVEN		3

#define CAM_CC_PLL2			4

#define CAM_CC_PLL2_OUT_MAIN		5

#define CAM_CC_PLL3			6

#define CAM_CC_BPS_AHB_CLK		7

#define CAM_CC_BPS_AREG_CLK		8

#define CAM_CC_BPS_AXI_CLK		9

#define CAM_CC_BPS_CLK			10

#define CAM_CC_BPS_CLK_SRC		11

#define CAM_CC_CAMNOC_ATB_CLK		12

#define CAM_CC_CAMNOC_AXI_CLK		13

#define CAM_CC_CCI_0_CLK		14

#define CAM_CC_CCI_0_CLK_SRC		15

#define CAM_CC_CCI_1_CLK		16

#define CAM_CC_CCI_1_CLK_SRC		17

#define CAM_CC_CORE_AHB_CLK		18

#define CAM_CC_CPAS_AHB_CLK		19

#define CAM_CC_CPHY_RX_CLK_SRC		20

#define CAM_CC_CSI0PHYTIMER_CLK		21

#define CAM_CC_CSI0PHYTIMER_CLK_SRC	22

#define CAM_CC_CSI1PHYTIMER_CLK		23

#define CAM_CC_CSI1PHYTIMER_CLK_SRC	24

#define CAM_CC_CSI2PHYTIMER_CLK		25

#define CAM_CC_CSI2PHYTIMER_CLK_SRC	26

#define CAM_CC_CSI3PHYTIMER_CLK		27

#define CAM_CC_CSI3PHYTIMER_CLK_SRC	28

#define CAM_CC_CSIPHY0_CLK		29

#define CAM_CC_CSIPHY1_CLK		30

#define CAM_CC_CSIPHY2_CLK		31

#define CAM_CC_CSIPHY3_CLK		32

#define CAM_CC_FAST_AHB_CLK_SRC		33

#define CAM_CC_ICP_APB_CLK		34

#define CAM_CC_ICP_ATB_CLK		35

#define CAM_CC_ICP_CLK			36

#define CAM_CC_ICP_CLK_SRC		37

#define CAM_CC_ICP_CTI_CLK		38

#define CAM_CC_ICP_TS_CLK		39

#define CAM_CC_IFE_0_AXI_CLK		40

#define CAM_CC_IFE_0_CLK		41

#define CAM_CC_IFE_0_CLK_SRC		42

#define CAM_CC_IFE_0_CPHY_RX_CLK	43

#define CAM_CC_IFE_0_CSID_CLK		44

#define CAM_CC_IFE_0_CSID_CLK_SRC	45

#define CAM_CC_IFE_0_DSP_CLK		46

#define CAM_CC_IFE_1_AXI_CLK		47

#define CAM_CC_IFE_1_CLK		48

#define CAM_CC_IFE_1_CLK_SRC		49

#define CAM_CC_IFE_1_CPHY_RX_CLK	50

#define CAM_CC_IFE_1_CSID_CLK		51

#define CAM_CC_IFE_1_CSID_CLK_SRC	52

#define CAM_CC_IFE_1_DSP_CLK		53

#define CAM_CC_IFE_2_AXI_CLK		54

#define CAM_CC_IFE_2_CLK		55

#define CAM_CC_IFE_2_CLK_SRC		56

#define CAM_CC_IFE_2_CPHY_RX_CLK	57

#define CAM_CC_IFE_2_CSID_CLK		58

#define CAM_CC_IFE_2_CSID_CLK_SRC	59

#define CAM_CC_IFE_2_DSP_CLK		60

#define CAM_CC_IFE_LITE_CLK		61

#define CAM_CC_IFE_LITE_CLK_SRC		62

#define CAM_CC_IFE_LITE_CPHY_RX_CLK	63

#define CAM_CC_IFE_LITE_CSID_CLK	64

#define CAM_CC_IFE_LITE_CSID_CLK_SRC	65

#define CAM_CC_IPE_0_AHB_CLK		66

#define CAM_CC_IPE_0_AREG_CLK		67

#define CAM_CC_IPE_0_AXI_CLK		68

#define CAM_CC_IPE_0_CLK		69

#define CAM_CC_IPE_0_CLK_SRC		70

#define CAM_CC_JPEG_CLK			71

#define CAM_CC_JPEG_CLK_SRC		72

#define CAM_CC_LRME_CLK			73

#define CAM_CC_LRME_CLK_SRC		74

#define CAM_CC_MCLK0_CLK		75

#define CAM_CC_MCLK0_CLK_SRC		76

#define CAM_CC_MCLK1_CLK		77

#define CAM_CC_MCLK1_CLK_SRC		78

#define CAM_CC_MCLK2_CLK		79

#define CAM_CC_MCLK2_CLK_SRC		80

#define CAM_CC_MCLK3_CLK		81

#define CAM_CC_MCLK3_CLK_SRC		82

#define CAM_CC_MCLK4_CLK		83

#define CAM_CC_MCLK4_CLK_SRC		84

#define CAM_CC_SLOW_AHB_CLK_SRC		85

#define CAM_CC_SOC_AHB_CLK		86

#define CAM_CC_SYS_TMR_CLK		87



#endif

include/dt-bindings/clock/qcom,dispcc-lagoon.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_LAGOON_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_LAGOON_H



/* DISP_CC clocks */

#define DISP_CC_PLL0				0

#define DISP_CC_MDSS_AHB_CLK			1

#define DISP_CC_MDSS_AHB_CLK_SRC		2

#define DISP_CC_MDSS_BYTE0_CLK			3

#define DISP_CC_MDSS_BYTE0_CLK_SRC		4

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC		5

#define DISP_CC_MDSS_BYTE0_INTF_CLK		6

#define DISP_CC_MDSS_DP_AUX_CLK			7

#define DISP_CC_MDSS_DP_AUX_CLK_SRC		8

#define DISP_CC_MDSS_DP_CRYPTO_CLK		9

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC		10

#define DISP_CC_MDSS_DP_LINK_CLK		11

#define DISP_CC_MDSS_DP_LINK_CLK_SRC		12

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC	13

#define DISP_CC_MDSS_DP_LINK_INTF_CLK		14

#define DISP_CC_MDSS_DP_PIXEL_CLK		15

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC		16

#define DISP_CC_MDSS_ESC0_CLK			17

#define DISP_CC_MDSS_ESC0_CLK_SRC		18

#define DISP_CC_MDSS_MDP_CLK			19

#define DISP_CC_MDSS_MDP_CLK_SRC		20

#define DISP_CC_MDSS_MDP_LUT_CLK		21

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK		22

#define DISP_CC_MDSS_PCLK0_CLK			23

#define DISP_CC_MDSS_PCLK0_CLK_SRC		24

#define DISP_CC_MDSS_ROT_CLK			25

#define DISP_CC_MDSS_ROT_CLK_SRC		26

#define DISP_CC_MDSS_RSCC_AHB_CLK		27

#define DISP_CC_MDSS_RSCC_VSYNC_CLK		28

#define DISP_CC_MDSS_VSYNC_CLK			29

#define DISP_CC_MDSS_VSYNC_CLK_SRC		30

#define DISP_CC_SLEEP_CLK			31

#define DISP_CC_XO_CLK				32



#endif

include/dt-bindings/clock/qcom,gcc-lagoon.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LAGOON_H

#define _DT_BINDINGS_CLK_QCOM_GCC_LAGOON_H



/* GCC clocks */

#define GPLL0					0

#define GPLL0_OUT_EVEN				1

#define GPLL0_OUT_ODD				2

#define GPLL6					3

#define GPLL6_OUT_EVEN				4

#define GPLL7					5

#define GCC_AGGRE_CNOC_PERIPH_CENTER_AHB_CLK	6

#define GCC_AGGRE_NOC_CENTER_AHB_CLK		7

#define GCC_AGGRE_NOC_PCIE_SF_AXI_CLK		8

#define GCC_AGGRE_NOC_PCIE_TBU_CLK		9

#define GCC_AGGRE_NOC_WLAN_AXI_CLK		10

#define GCC_AGGRE_UFS_PHY_AXI_CLK		11

#define GCC_AGGRE_USB3_PRIM_AXI_CLK		12

#define GCC_BOOT_ROM_AHB_CLK			13

#define GCC_CAMERA_AHB_CLK			14

#define GCC_CAMERA_AXI_CLK			15

#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK		16

#define GCC_CAMERA_THROTTLE_RT_AXI_CLK		17

#define GCC_CAMERA_XO_CLK			18

#define GCC_CE1_AHB_CLK				19

#define GCC_CE1_AXI_CLK				20

#define GCC_CE1_CLK				21

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		22

#define GCC_CPUSS_AHB_CLK			23

#define GCC_CPUSS_AHB_CLK_SRC			24

#define GCC_CPUSS_AHB_DIV_CLK_SRC		25

#define GCC_CPUSS_GNOC_CLK			26

#define GCC_CPUSS_RBCPR_CLK			27

#define GCC_DDRSS_GPU_AXI_CLK			28

#define GCC_DISP_AHB_CLK			29

#define GCC_DISP_AXI_CLK			30

#define GCC_DISP_CC_SLEEP_CLK			31

#define GCC_DISP_CC_XO_CLK			32

#define GCC_DISP_GPLL0_CLK			33

#define GCC_DISP_THROTTLE_AXI_CLK		34

#define GCC_DISP_XO_CLK				35

#define GCC_GP1_CLK				36

#define GCC_GP1_CLK_SRC				37

#define GCC_GP2_CLK				38

#define GCC_GP2_CLK_SRC				39

#define GCC_GP3_CLK				40

#define GCC_GP3_CLK_SRC				41

#define GCC_GPU_CFG_AHB_CLK			42

#define GCC_GPU_GPLL0_CLK			43

#define GCC_GPU_GPLL0_DIV_CLK			44

#define GCC_GPU_MEMNOC_GFX_CLK			45

#define GCC_GPU_SNOC_DVM_GFX_CLK		46

#define GCC_NPU_AXI_CLK				47

#define GCC_NPU_BWMON_AXI_CLK			48

#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK		49

#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK		50

#define GCC_NPU_CFG_AHB_CLK			51

#define GCC_NPU_DMA_CLK				52

#define GCC_NPU_GPLL0_CLK			53

#define GCC_NPU_GPLL0_DIV_CLK			54

#define GCC_PCIE_0_AUX_CLK			55

#define GCC_PCIE_0_AUX_CLK_SRC			56

#define GCC_PCIE_0_CFG_AHB_CLK			57

#define GCC_PCIE_0_MSTR_AXI_CLK			58

#define GCC_PCIE_0_PIPE_CLK			59

#define GCC_PCIE_0_SLV_AXI_CLK			60

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK		61

#define GCC_PCIE_PHY_RCHNG_CLK			62

#define GCC_PCIE_PHY_RCHNG_CLK_SRC		63

#define GCC_PDM2_CLK				64

#define GCC_PDM2_CLK_SRC			65

#define GCC_PDM_AHB_CLK				66

#define GCC_PDM_XO4_CLK				67

#define GCC_PRNG_AHB_CLK			68

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		69

#define GCC_QUPV3_WRAP0_CORE_CLK		70

#define GCC_QUPV3_WRAP0_S0_CLK			71

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		72

#define GCC_QUPV3_WRAP0_S1_CLK			73

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		74

#define GCC_QUPV3_WRAP0_S2_CLK			75

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		76

#define GCC_QUPV3_WRAP0_S3_CLK			77

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		78

#define GCC_QUPV3_WRAP0_S4_CLK			79

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		80

#define GCC_QUPV3_WRAP0_S5_CLK			81

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		82

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		83

#define GCC_QUPV3_WRAP1_CORE_CLK		84

#define GCC_QUPV3_WRAP1_S0_CLK			85

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		86

#define GCC_QUPV3_WRAP1_S1_CLK			87

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		88

#define GCC_QUPV3_WRAP1_S2_CLK			89

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		90

#define GCC_QUPV3_WRAP1_S3_CLK			91

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		92

#define GCC_QUPV3_WRAP1_S4_CLK			93

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		94

#define GCC_QUPV3_WRAP1_S5_CLK			95

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		96

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		97

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		98

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		99

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		100

#define GCC_SDCC1_AHB_CLK			101

#define GCC_SDCC1_APPS_CLK			102

#define GCC_SDCC1_APPS_CLK_SRC			103

#define GCC_SDCC1_ICE_CORE_CLK			104

#define GCC_SDCC1_ICE_CORE_CLK_SRC		105

#define GCC_SDCC2_AHB_CLK			106

#define GCC_SDCC2_APPS_CLK			107

#define GCC_SDCC2_APPS_CLK_SRC			108

#define GCC_SYS_NOC_CPUSS_AHB_CLK		109

#define GCC_UFS_MEM_CLKREF_CLK			110

#define GCC_UFS_PHY_AHB_CLK			111

#define GCC_UFS_PHY_AXI_CLK			112

#define GCC_UFS_PHY_AXI_CLK_SRC			113

#define GCC_UFS_PHY_ICE_CORE_CLK		114

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		115

#define GCC_UFS_PHY_PHY_AUX_CLK			116

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		117

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		118

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK		119

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		120

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		121

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		122

#define GCC_USB30_PRIM_MASTER_CLK		123

#define GCC_USB30_PRIM_MASTER_CLK_SRC		124

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		125

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	126

#define GCC_USB30_PRIM_MOCK_UTMI_DIV_CLK_SRC	127

#define GCC_USB3_PRIM_CLKREF_CLK		128

#define GCC_USB30_PRIM_SLEEP_CLK		129

#define GCC_USB3_PRIM_PHY_AUX_CLK		130

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		131

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		132

#define GCC_USB3_PRIM_PHY_PIPE_CLK		133

#define GCC_VIDEO_AHB_CLK			134

#define GCC_VIDEO_AXI_CLK			135

#define GCC_VIDEO_THROTTLE_AXI_CLK		136

#define GCC_VIDEO_XO_CLK			137

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK		138

#define GCC_UFS_PHY_AXI_HW_CTL_CLK		139

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK	140

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK	141

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK		142



/* GCC resets */

#define GCC_QUSB2PHY_PRIM_BCR			0

#define GCC_QUSB2PHY_SEC_BCR			1

#define GCC_SDCC1_BCR				2

#define GCC_SDCC2_BCR				3

#define GCC_UFS_PHY_BCR				4

#define GCC_USB30_PRIM_BCR			5

#define GCC_PCIE_0_BCR				6

#define GCC_PCIE_0_PHY_BCR			7

#define GCC_QUPV3_WRAPPER_0_BCR			8

#define GCC_QUPV3_WRAPPER_1_BCR			9



#endif

include/dt-bindings/clock/qcom,gpucc-lagoon.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_LAGOON_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_LAGOON_H



/* GPU_CC clocks */

#define GPU_CC_PLL0						0

#define GPU_CC_PLL0_OUT_EVEN					1

#define GPU_CC_PLL1						2

#define GPU_CC_PLL1_OUT_EVEN					3

#define GPU_CC_ACD_AHB_CLK					4

#define GPU_CC_ACD_CXO_CLK					5

#define GPU_CC_AHB_CLK						6

#define GPU_CC_CRC_AHB_CLK					7

#define GPU_CC_CX_GFX3D_CLK					8

#define GPU_CC_CX_GFX3D_SLV_CLK					9

#define GPU_CC_CX_GMU_CLK					10

#define GPU_CC_CX_SNOC_DVM_CLK					11

#define GPU_CC_CXO_AON_CLK					12

#define GPU_CC_CXO_CLK						13

#define GPU_CC_GMU_CLK_SRC					14

#define GPU_CC_GX_CXO_CLK					15

#define GPU_CC_GX_GFX3D_CLK					16

#define GPU_CC_GX_GFX3D_CLK_SRC					17

#define GPU_CC_GX_GMU_CLK					18

#define GPU_CC_GX_VSENSE_CLK					19

#define GPU_CC_SLEEP_CLK					20



#endif

include/dt-bindings/clock/qcom,npucc-lagoon.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_LAGOON_H

#define _DT_BINDINGS_CLK_QCOM_NPU_CC_LAGOON_H



/* NPU_CC clocks */

#define NPU_CC_PLL0			0

#define NPU_CC_PLL0_OUT_EVEN		1

#define NPU_CC_PLL1			2

#define NPU_CC_PLL1_OUT_EVEN		3

#define NPU_CC_BTO_CORE_CLK		5

#define NPU_CC_BWMON_CLK		6

#define NPU_CC_CAL_HM0_CDC_CLK		7

#define NPU_CC_CAL_HM0_CLK		8

#define NPU_CC_CAL_HM0_CLK_SRC		9

#define NPU_CC_CAL_HM0_PERF_CNT_CLK	10

#define NPU_CC_CORE_CLK			11

#define NPU_CC_CORE_CLK_SRC		12

#define NPU_CC_DSP_AHBM_CLK		13

#define NPU_CC_DSP_AHBS_CLK		14

#define NPU_CC_DSP_AXI_CLK		15

#define NPU_CC_NOC_AHB_CLK		16

#define NPU_CC_NOC_AXI_CLK		17

#define NPU_CC_NOC_DMA_CLK		18

#define NPU_CC_RSC_XO_CLK		19

#define NPU_CC_S2P_CLK			20

#define NPU_CC_XO_CLK			21

#define NPU_CC_XO_CLK_SRC		22

#define NPU_DSP_CORE_CLK_SRC		23

#define NPU_Q6SS_PLL			24



/* NPU_CC resets */

#define NPU_CC_CAL_HM0_BCR		0

#define NPU_CC_CORE_BCR			1

#define NPU_CC_DSP_BCR			2



#endif