Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 33440d3c authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: qcom: Update bw table and iommu properties on msm8937 GPU"

parents 7215d79e 3e514a91

qcom/msm8917-gpu.dtsi

+23 −15
Original line number Diff line number Diff line
@@ -4,26 +4,34 @@ 
		compatible = "qcom,kgsl-busmon";

	};



	gpu_bw_tbl: gpu-bw-tbl {

		compatible = "operating-points-v2";

		opp-0    { opp-hz = /bits/ 64 < 0 >;     }; /* OFF */



		opp-201  { opp-hz = /bits/ 64 < 769 >;   }; /* 1.  201 MHz */



		opp-422  { opp-hz = /bits/ 64 < 1611 >;  }; /* 2.  422 MHz */



		opp-595  { opp-hz = /bits/ 64 < 2270 >;  }; /* 3.  595 MHz */



		opp-768  { opp-hz = /bits/ 64 < 2929 >;  }; /* 4.  768 MHz */



		opp-1113 { opp-hz = /bits/ 64 < 4248 >;  }; /* 5. 1113 MHz */



		opp-1190 { opp-hz = /bits/ 64 < 4541 >;  }; /* 6. 1190 MHz */



		opp-1344 { opp-hz = /bits/ 64 < 5126 >;  }; /* 7. 1344 MHz */



		opp-1478 { opp-hz = /bits/ 64 < 5639 >;  }; /* 8. 1478 MHz */

	};



	/* Bus governor */

	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		/*

		 * Need to configure 2x Clock as BIMC

		 * Internally Divides by 2 for Gen1 DDR PHY.

		 */

		operating-points-v2 = <&gpu_bw_tbl>;

		qcom,active-only;

		qcom,bw-tbl =

			< 0 >,    /* Off */

			< 769 >,  /* 1. DDR:100.80 MHz BIMC: 201.60 MHz */

			< 1611 >, /* 2. DDR:211.20 MHz BIMC: 422.40 MHz */

			< 2270 >, /* 3. DDR:297.60 MHz BIMC: 595.20 MHz */

			< 2929 >, /* 4. DDR:384.00 MHz BIMC: 768.00 MHz */

			< 4248 >, /* 5. DDR:556.80 MHz BIMC: 1113.60 MHz */

			< 4541 >, /* 6. DDR:595.20 MHz BIMC: 1190.40 MHz */

			< 5126 >, /* 7. DDR:672.00 MHz BIMC: 1344.00 MHz */

			< 5639 >; /* 8. DDR:739.20 MHz BIMC: 1478.40 MHz */

	};



	msm_gpu: qcom,kgsl-3d0@1c00000 {
@@ -158,7 +166,6 @@ 
		 * The gpu can only program a single context bank

		 * at this fixed offset.

		 */

		qcom,protect = <0xa000 0x1000>;

		clocks = <&gcc GCC_SMMU_CFG_CLK>,

			<&gcc GCC_GFX_TCU_CLK>,

			<&gcc GCC_GTCU_AHB_CLK>,
@@ -169,6 +176,7 @@ 
		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&gfx_iommu 0>;

			qcom,iommu-dma = "disabled";

			qcom,gpu-offset = <0xa000>;

		};

	};

qcom/msm8937-gpu.dtsi

+27 −14
Original line number Diff line number Diff line
@@ -4,28 +4,42 @@ 
		compatible = "qcom,kgsl-busmon";

	};



	gpu_bw_tbl: gpu-bw-tbl {

		compatible = "operating-points-v2";

		opp-0    { opp-hz = /bits/ 64 < 0 >;     }; /* OFF */



		opp-201  { opp-hz = /bits/ 64 < 769 >;   }; /*  1. 201  MHz */



		opp-422  { opp-hz = /bits/ 64 < 1611 >;  }; /*  2. 422  MHz */



		opp-557  { opp-hz = /bits/ 64 < 2124 >;  }; /*  3. 557  MHz */



		opp-768  { opp-hz = /bits/ 64 < 2929 >;  }; /*  4. 768  MHz */



		opp-1075 { opp-hz = /bits/ 64 < 4101 >;  }; /*  5. 1075 MHz */



		opp-1113 { opp-hz = /bits/ 64 < 4248 >;  }; /*  6. 1113 MHz */



		opp-1401 { opp-hz = /bits/ 64 < 5346 >;  }; /*  7. 1401 MHz */



		opp-1497 { opp-hz = /bits/ 64 < 5712 >;  }; /*  8. 1497 MHz */



		opp-1613 { opp-hz = /bits/ 64 < 6152 >;  }; /*  9. 1613 MHz */



		opp-1843 { opp-hz = /bits/ 64 < 7031 >;  }; /* 10. 1843 MHz */

	};



	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		operating-points-v2 = <&gpu_bw_tbl>;

		/*

		 * active-only flag is used while registering the bus

		 * governor.It helps release the bus vote when the CPU

		 * subsystem is inactiv3

		 */

		qcom,active-only;

		qcom,bw-tbl =

			< 0    >, /*  off */

			<  769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */

			< 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */

			< 2124 >, /* 3. DDR:278.40 MHz BIMC: 139.20 MHz */

			< 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */

			< 4101 >, /* 5. DDR:537.60 MHz BIMC: 268.80 MHz */

			< 4248 >, /* 6. DDR:556.80 MHz BIMC: 278.40 MHz */

			< 5346 >, /* 7. DDR:662.40 MHz BIMC: 331.20 MHz */

			< 5712 >, /* 8. DDR:748.80 MHz BIMC: 374.40 MHz */

			< 6152 >, /* 9. DDR:806.40 MHz BIMC: 403.20 MHz */

			< 7031 >; /* 10. DDR:921.60 MHz BIMC: 460.80 MHz */

	};



	msm_gpu: qcom,kgsl-3d0@1c00000 {
@@ -214,8 +228,6 @@ 
		compatible = "qcom,kgsl-smmu-v2";



		reg = <0x1c40000 0x10000>;

		qcom,protect = <0x40000 0x10000>;

		qcom,micro-mmu-control = <0x6000>;



		clocks = <&gcc GCC_OXILI_AHB_CLK>,

			 <&gcc GCC_BIMC_GFX_CLK>;
@@ -228,6 +240,7 @@ 
			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0>;

			qcom,iommu-dma = "disabled";

			qcom,gpu-offset = <0x48000>;

		};

	};