RISC-V: Preliminary Perf Support

The RISC-V ISA defines a core set of performance counters that must
exist on all processors along with a standard way to add more
performance counters.

This patch set adds preliminary perf support for RISC-V systems.  Long
term we'll move to model where all PMUs can be built into the kernel at
the same time, detected at runtime (possibly via device tree), and
provided to userspace.  Since we currently only support the ISA-mandated
performance counters there's no need to detect anything right now.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>