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Commit 32a47e72 authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller
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qed: Add CONFIG_QED_SRIOV



Add support for a new Kconfig option for qed* driver which would allow
[eventually] the support in VFs.

This patch adds the necessary logic in the PF to learn about the possible
VFs it will have to support [Based on PCI configuration space and HW],
and prepare a database with an entry per-VF as infrastructure for future
interaction with said VFs.

Signed-off-by: default avatarYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 631ad4a3
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+10 −0
Original line number Diff line number Diff line
@@ -98,6 +98,16 @@ config QED
	---help---
	  This enables the support for ...

config QED_SRIOV
	bool "QLogic QED 25/40/100Gb SR-IOV support"
	depends on QED && PCI_IOV
	default y
	---help---
	  This configuration parameter enables Single Root Input Output
	  Virtualization support for QED devices.
	  This allows for virtual function acceleration in virtualized
	  environments.

config QEDE
	tristate "QLogic QED 25/40/100Gb Ethernet NIC"
	depends on QED
+1 −0
Original line number Diff line number Diff line
@@ -3,3 +3,4 @@ obj-$(CONFIG_QED) := qed.o
qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
	 qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \
	 qed_selftest.o
qed-$(CONFIG_QED_SRIOV) += qed_sriov.o
+7 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ enum QED_RESOURCES {

enum QED_FEATURE {
	QED_PF_L2_QUE,
	QED_VF,
	QED_MAX_FEATURES,
};

@@ -360,6 +361,7 @@ struct qed_hwfn {
	/* True if the driver requests for the link */
	bool				b_drv_link_init;

	struct qed_pf_iov		*pf_iov_info;
	struct qed_mcp_info		*mcp_info;

	struct qed_hw_cid_data		*p_tx_cids;
@@ -484,6 +486,10 @@ struct qed_dev {
	u8				num_hwfns;
	struct qed_hwfn			hwfns[MAX_HWFNS_PER_DEVICE];

	/* SRIOV */
	struct qed_hw_sriov_info *p_iov_info;
#define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)

	unsigned long			tunn_mode;
	u32				drv_type;

@@ -514,6 +520,7 @@ struct qed_dev {
	const struct firmware		*firmware;
};

#define NUM_OF_VFS(dev)         MAX_NUM_VFS_BB
#define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
#define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB

+19 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@
#include "qed_mcp.h"
#include "qed_reg_addr.h"
#include "qed_sp.h"
#include "qed_sriov.h"

/* API common to all protocols */
enum BAR_ID {
@@ -136,6 +137,7 @@ void qed_resc_free(struct qed_dev *cdev)
		qed_eq_free(p_hwfn, p_hwfn->p_eq);
		qed_consq_free(p_hwfn, p_hwfn->p_consq);
		qed_int_free(p_hwfn);
		qed_iov_free(p_hwfn);
		qed_dmae_info_free(p_hwfn);
	}
}
@@ -316,6 +318,10 @@ int qed_resc_alloc(struct qed_dev *cdev)
		if (rc)
			goto alloc_err;

		rc = qed_iov_alloc(p_hwfn);
		if (rc)
			goto alloc_err;

		/* EQ */
		p_eq = qed_eq_alloc(p_hwfn, 256);
		if (!p_eq) {
@@ -373,6 +379,8 @@ void qed_resc_setup(struct qed_dev *cdev)
		       p_hwfn->mcp_info->mfw_mb_length);

		qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);

		qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
	}
}

@@ -1238,6 +1246,13 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
	u32 port_mode;
	int rc;

	/* Since all information is common, only first hwfns should do this */
	if (IS_LEAD_HWFN(p_hwfn)) {
		rc = qed_iov_hw_info(p_hwfn);
		if (rc)
			return rc;
	}

	/* Read the port mode */
	port_mode = qed_rd(p_hwfn, p_ptt,
			   CNIG_REG_NW_PORT_MODE_BB_B0);
@@ -1397,6 +1412,8 @@ static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,

	return rc;
err2:
	if (IS_LEAD_HWFN(p_hwfn))
		qed_iov_free_hw_info(p_hwfn->cdev);
	qed_mcp_free(p_hwfn);
err1:
	qed_hw_hwfn_free(p_hwfn);
@@ -1463,6 +1480,8 @@ void qed_hw_remove(struct qed_dev *cdev)
		qed_hw_hwfn_free(p_hwfn);
		qed_mcp_free(p_hwfn);
	}

	qed_iov_free_hw_info(cdev);
}

int qed_chain_alloc(struct qed_dev *cdev,
+11 −0
Original line number Diff line number Diff line
@@ -338,6 +338,17 @@ void qed_port_unpretend(struct qed_hwfn *p_hwfn,
	       *(u32 *)&p_ptt->pxp.pretend);
}

u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid)
{
	u32 concrete_fid = 0;

	SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
	SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
	SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);

	return concrete_fid;
}

/* DMAE */
static void qed_dmae_opcode(struct qed_hwfn *p_hwfn,
			    const u8 is_src_type_grc,
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