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Commit 327432c2 authored by Christoffer Dall's avatar Christoffer Dall Committed by Marc Zyngier
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KVM: arm/arm64: vgic: Update documentation of the GIC devices wrt IIDR 



Update the documentation to reflect the ordering requirements of
restoring the GICD_IIDR register before any other registers and the
effects this has on restoring the interrupt groups for an emulated GICv2
instance.

Also remove some outdated limitations in the documentation while we're
at it.

Reviewed-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 32f8777e

Documentation/virtual/kvm/devices/arm-vgic-v3.txt

+8 −0
Original line number Diff line number Diff line
@@ -100,6 +100,14 @@ Groups: 
    Note that distributor fields are not banked, but return the same value

    regardless of the mpidr used to access the register.



    GICD_IIDR.Revision is updated when the KVM implementation is changed in a

    way directly observable by the guest or userspace.  Userspace should read

    GICD_IIDR from KVM and write back the read value to confirm its expected

    behavior is aligned with the KVM implementation.  Userspace should set

    GICD_IIDR before setting any other registers to ensure the expected

    behavior.





    The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such

    that a write of a clear bit has no effect, whereas a write with a set bit

    clears that value.  To allow userspace to freely set the values of these two

Documentation/virtual/kvm/devices/arm-vgic.txt

+9 −6
Original line number Diff line number Diff line
@@ -49,9 +49,15 @@ Groups: 
    index is specified with the vcpu_index field.  Note that most distributor

    fields are not banked, but return the same value regardless of the

    vcpu_index used to access the register.

  Limitations:

    - Priorities are not implemented, and registers are RAZ/WI

    - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.



    GICD_IIDR.Revision is updated when the KVM implementation of an emulated

    GICv2 is changed in a way directly observable by the guest or userspace.

    Userspace should read GICD_IIDR from KVM and write back the read value to

    confirm its expected behavior is aligned with the KVM implementation.

    Userspace should set GICD_IIDR before setting any other registers (both

    KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure

    the expected behavior. Unless GICD_IIDR has been set from userspace, writes

    to the interrupt group registers (GICD_IGROUPR) are ignored.

  Errors:

    -ENXIO: Getting or setting this register is not yet supported

    -EBUSY: One or more VCPUs are running
@@ -94,9 +100,6 @@ Groups: 
    use the lower 5 bits to communicate with the KVM device and must shift the

    value left by 3 places to obtain the actual priority mask level.



  Limitations:

    - Priorities are not implemented, and registers are RAZ/WI

    - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.

  Errors:

    -ENXIO: Getting or setting this register is not yet supported

    -EBUSY: One or more VCPUs are running