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Commit 3230e837 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add gladiator support for bengal"

parents 24497687 e75f5b8c

bindings/arm/msm/msm_gladiator_erp.txt

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+21 −0
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* MSM Gladiator error reporting driver



Required properties:

- compatible: Should be "qcom,msm-gladiator" or "qcom,msm-gladiator-v2" or

"qcom,msm-gladiator-v3"

- reg: I/O address Gladiator H/W block

- reg-names: Should be "gladiator_base"

- interrupts: Should contain the gladiator error interrupt number

- clock-names: Should be "atb_clk"

- clocks: Handles to clocks specified in "clock-names" property.



Example:



qcom,msm-gladiator-v2@b1c0000 {

	compatible = "qcom,msm-gladiator";

	reg = <0xb1c0000 0xe000>;

	reg-names = "gladiator_base";

	interrupts = <0 34 0>;

	clock-names = "atb_clk";

	clocks = <&clock_gcc clk_qdss_clk>;

}

bindings/edac/arm64_cache_erp.txt

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* ARM Cortex A53 / A57 cache error reporting driver



Required properties:

- compatible: Should be "arm,arm64-cpu-erp"

- interrupts: List of hardware interrupts that may indicate an error condition

  in the CPU subsystem, or in the L1 / L2 caches. At least one interrupt entry

  is required.

- interrupt-names: Must contain one or more of the following IRQ types:

	"pri-dbe-irq" - double-bit error interrupt for primary cluster

	"sec-dbe-irq" - double-bit error interrupt for secondary cluster

	"pri-ext-irq" - external bus error interrupt for primary cluster

	"sec-ext-irq" - external bus error interrupt for secondary cluster

	"cci-irq"     - CCI error interrupt. If this property is present, having

			the 'cci' reg-base defined using the 'reg' property is

			recommended.

	At least one irq entry is required.



Optional properties:

- reg: Should contain physical address of the CCI register space

- reg-names: Should contain 'cci'. Must be present if 'reg' property is present

- poll-delay-msec: Indicates how often the edac check callback should be called. Time in msec.



Example:

	cpu_cache_erp {

		compatible = "arm,arm64-cpu-erp";

		interrupt-names = "pri-dbe-irq",

				  "sec-dbe-irq",

				  "pri-ext-irq",

				  "sec-ext-irq";

		interrupts = <0 92 0>,

			     <0 91 0>,

			     <0 96 0>,

			     <0 95 0>;

	};

qcom/bengal.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -586,6 +586,19 @@ 
		};

	};



	arm64_cpu_erp {

		compatible = "arm,arm64-cpu-erp";

		interrupt-names = "pri-dbe-irq",

				  "sec-dbe-irq",

				  "pri-ext-irq",

				  "sec-ext-irq";

		interrupts = <0 43 4>,

			     <0 44 4>,

			     <0 41 4>,

			     <0 42 4>;

		poll-delay-ms = <5000>;

	};



	qcom,msm-imem@c125000 {

		compatible = "qcom,msm-imem";

		reg = <0xc125000 0x1000>;
@@ -647,6 +660,32 @@ 
		qcom,rtb-size = <0x100000>;

	};



	cpu_pmu: cpu-pmu {

		compatible = "arm,armv8-pmuv3";

		qcom,irq-is-percpu;

		interrupts = <1 6 4>;

	};



	eud: qcom,msm-eud@1610000 {

		compatible = "qcom,msm-eud";

		interrupt-names = "eud_irq";

		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;

		reg = <0x1610000 0x2000>,

		      <0x1612000 0x1000>;

		reg-names = "eud_base", "eud_mode_mgr2";

		qcom,secure-eud-en;

		status = "ok";

	};



	qcom,msm-gladiator-v2@f100000 {

		compatible = "qcom,msm-gladiator-v2";

		reg = <0xf100000 0xdc00>;

		reg-names = "gladiator_base";

		interrupts = <0 22 0>;

		clock-names = "atb_clk";

		clocks = <&rpmcc RPM_QDSS_CLK>;

	};



	wdog: qcom,wdt@f017000 {

		compatible = "qcom,msm-watchdog";

		reg = <0xf017000 0x1000>;